Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
Reexamination Certificate
2001-08-07
2004-02-10
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Incrementing, decrementing, or shifting circuitry
C711S212000, C712S032000
Reexamination Certificate
active
06691219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to integrated circuit devices and, more particularly, to microcontrollers.
2. Description of Related Art
Processing units of electronic devices may be broadly divided into two categories: (i) processors used as central processing units (CPUs) of (e.g., personal) computers and (ii) embedded processors (a.k.a. microcontrollers, microprocessors, etc.) (e.g., processors operating in cars, microwaves, wireless phones, industrial equipment, televisions, other consumer electronic devices, etc.). Although CPUs are more well-known than microcontrollers, CPU's are actually only responsible for less than 1% of all processors sold, while microcontrollers are responsible for greater than 99% of all processors sold. Consequently, significant time and money is expended for research and development to improve the efficiency, speed, security, feature set, etc. of microcontrollers.
One type of microcontroller is an 8-bit microcontroller, of which the 8051 microcontroller is one example. The term “8051” hereinafter includes any microcontroller that executes at least a substantial portion of the well-known 8051 instruction set. Such 8-bit microcontrollers are used extensively in products today because of their small size, low power consumption, and flexibility. In addition, since the market for 8-bit microcontrollers continues to grow, silicon manufacturers are pushing the development of faster, more efficient 8-bit microcontrollers.
High-Speed 8051 Microcontrollers are a family of 8051-compatible microcontrollers providing increased performance compared to the traditional 8051 family. High-Speed 8051 Micros are 100% instruction set and object code compatible with the Intel 8051 core. To make faster 8051 microcontrollers, designers have implemented more efficient code, faster clocks, and circuits to handle the faster speeds. However, even with the increased speed, many programmers are now demanding that 8051 microcontrollers also support high-level language programming, such as C and C++.
In order to support high-level language programming, more memory and expanded addressing capability are required. Currently, 8051 microcontrollers use 16-bit addressing with 64 K bytes of memory. In order to increase the addressing up to 24-bits with 16M bytes of memory, other designers have increased the internal data bus to 16-bits and extensively modified the 8051 instruction set to accommodate a larger internal bus. However, the new “16-bit” microcontrollers are expensive due to the increased silicon area and circuitry involved in supporting a 16-bit internal bus. In addition, since the new “16-bit” microcontrollers use a modified instruction set, the software must be re-compiled to run on the “16-bit” microcontroller, and the user must learn the new modified instruction set. Furthermore, 16-bit microcontrollers consume more power than 8-bit microcontrollers. Therefore, there is a need for an 8-bit microcontroller with expanded addressing capability.
SUMMARY OF THE INVENTION
The deficiencies of the prior art are overcome by the methods, systems, and arrangements of the present invention. The present invention provides an 8-bit microcontroller with an 8-bit internal bus capable of supporting expanded addressing capability in one of three address modes. Specifically, the microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16 M bytes of program memory and 16 M bytes of data memory to be supported via a new Address Page (AP) Special Function Register (SFR), a new first extended data pointer (DPX) Special Function Register and a new second extended data pointer (DPX1) Special Function Register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to eight basic instructions.
In embodiments of the present invention, in the 24-bit paged mode, the upper third byte of the Program Counter is not incremented when the lower 16 bits in the lower two bytes of the Program Counter roll over from FFFFh to 0000h. Thus, in the 24-bit paged address mode, the third byte of the Program Counter functions only as a storage register which is loaded by the AP register whenever the processor executes an instruction. Similarly, for addressing data memory, the logic value in the upper third byte of the data pointer register is not incremented or decremented when the lower 16 bits in the lower two bytes of the selected data pointer are overflowed or underflowed. Furthermore, execution of program counter or data pointer related instructions in the paged address mode is limited to the 64 K byte page that is pointed to by the current contents of the upper third byte of the program counter or data pointer register.
In further embodiments of the present invention, the 24-bit contiguous address mode is supported by a full 24-bit Program Counter and 24-bit data pointer with a limited set of eight modified instructions that operate in the 24-bit address range. All instruction opcodes retain identical binary compatibility to the 8051 instruction set, and the modified instructions are only different with respect to their cycle and/or byte/operand count.
In still further embodiments of the present invention, an extended program stack is provided that is capable of addressing up to 1 K bytes of stack memory with a programmable option. In a first stack option, an 8-bit Stack Pointer addresses a stack size of 256 bytes that is located in the Scratchpad RAM area. In a second stack option, a 10-bit Stack Pointer addresses the extended 1K program stack located in the internal data memory area.
REFERENCES:
patent: 5659703 (1997-08-01), Moore et al.
patent: 6502181 (2002-12-01), MacKenna et al.
Grider Stephen N.
Little Ann
Little Wendell L.
Ma Edward Tangkwai
Taylor, III Frank V.
Bragdon Reginald G.
Dallas Semiconductor Corporation
Jenkens & Gilchrist A Profesional Corporation
Little Ann
Vital Pierre M.
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