Method and apparatus for 1-T SRAM compatible memory

Details Method and apparatus for 1-T SRAM compatible memory Method and apparatus for 1-T SRAM compatible memory

1998-03-09

2000-02-22

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

365195, G11C 700

Patent

active

060288043

ABSTRACT:
A method and apparatus for handling the refresh of a DRAM array so that the refresh has no effect on the external access. This allows an SRAM compatible memory to be built from DRAM (or 1-Transistor) cells. By utilizing the unused external access time for performing the infrequent memory refresh, there is no penalty on the peak bandwidth requirement of the memory array.

REFERENCES:
patent: 4549284 (1985-10-01), Ikuzaki
patent: 4625301 (1986-11-01), Berger
patent: 5511033 (1996-04-01), Jung
patent: 5544120 (1996-08-01), Kuwagata et al.
patent: 5586287 (1996-12-01), Okumura et al.

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