Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-05-24
2001-08-21
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S189020, C327S259000
Reexamination Certificate
active
06278641
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88118042, filed Oct. 19, 1999.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method and apparatus for accessing data from a dynamic access random memory (DRAM) of a computer. More particularly, the present invention relates to a method and apparatus capable of programmably delaying a clock of memory.
2. Description of Related Art
The main memory of a computer, such as a personal computer (PC), is used for storing data or information, which can be accessed by a central processing unit (CPU) of the PC. Namely, data can be stored within and read from the main memory and furthermore, program and data are executed or processed within the memory. Accompanying highly developed semiconductor technology, it is common for a modem PC to have tens or hundreds of megabytes (MB) of memory. In addition, the clock frequency of the memory rises up to 100 MHz or higher as the clock frequency of the CPU continuously increases.
As the clock frequency of the memory rises, the clock period of the memory is shortened. In addition, the clock sent from the north bridge (NB) of a PC is transmitted to the memory module, which is delayed when it passes through a transmission path on a print circuit board (PCB). When a memory module senses the command word asserted by the NB according to the rising edge of the clock, the memory module can't correctly read the command word because there is not enough setup time, which causes the PC to malfunction.
FIG. 1
is a schematic block diagram of a north bridge (NB) and DRAM module of a conventional PC. As shown in
FIG. 1
, the NB
10
comprises a phase locked loop (PLL) circuit
11
having two inputs for respectively receiving a command output clock signal (DCLK) and a feedback input clock signal (DCLKIN), which both have the same phase and frequency, and an output for outputting a bus output clock signal (DCLKO), which has the same frequency of DCLK but leads the DCLK by one phase. DCLKO is transmitted to the DRAM module
20
through a transmission path, and is fed back to PLL circuit
11
by the transmission path serving as signal DCLKIN. Because the transmission delay is substantially equal, the frequency and phase of DCLKIN detected at the input of PLL circuit is substantially equal to those of the memory input clock signal (CLK_DM) detected at the DRAM module
20
.
FIG. 2A
depicts a timing diagram of the north bridge when the north bridge accesses the DRAM module according to a conventional PC architecture. The command output clock signal DCLK is sent from the north bridge. Referring to
FIGS. 1
,
2
A and
2
B, at time T1, the north bridge
10
asserts a command word (CMD) to DRAM module
20
, and the phase of the command word received at the DRAM module
20
is slightly delayed due to the transmission delay. As a result, there is not enough setup time while the DRAM module
20
tries to sense the command word CMD_DM at the rising edge of time T2 of memory input clock signal CLK_DM. This makes it impossible for the DRAM module
20
to send out correct data at time T3. Furthermore, the NB also lacks sufficient setup time to sense and read data from DRAM module
20
due to the transmission delay. Therefore, the NB
10
is unable to sense and read data from DRAM module
20
. The situation is more serious when the memory is operated at a high speed or with heavy loading.
SUMMARY OF THE INVENTION
The invention provides an apparatus capable of programmably delaying a clock of a DRAM. The clock of the DRAM or the internal clock of the north bridge can be selectively delayed or not by means of the basic input output system (BIOS), external electric switches or other logic devices. Therefore, the DRAM module has enough setup time at the rising edge of a work clock to correctly read the command word. The north bridge can then correctly receive data from the DRAM module and transfer the data to the CPU or an accelerating graphic port (AGP).
The invention provides an apparatus capable of programmably delaying a clock of a DRAM. The clock of the DRAM can be selectively delayed or not by means of the BIOS, external electric switches or other logic devices. Therefore, the DRAM module has enough setup time at the rising edge of the work clock to correctly read out the command word, by which a computer can function normally.
The invention provides a method capable of programmably delaying a clock of a DRAM. The clock of the DRAM or the internal clock of the north bridge can be selectively delayed or not by means of the BIOS, external electric switches or other logic devices. Therefore, the DRAM module has enough setup time at the rising edge of the work clock to correctly read out the command word. The north bridge can then correctly receive data from the DRAM module and transfer the data to the CPU or AGP.
The invention provides an apparatus capable of programmably delaying a clock of a DRAM, which is suitable for a chipset, such as a north bridge chipset (north bridge or NB). The apparatus comprises a first delay means for delaying the output of a first internal clock signal by selecting an adequate delay time; a second multiplexer for selecting a second internal clock signal; a third multiplexer for selecting an adequate delay time to output the second internal clock signal; a fourth multiplexer for selecting an adequate delay time to output the first internal clock signal; and a phase locked loop (PLL) circuit for receiving the adequately delayed first and second internal clock signals to output a first output clock signal. The first output clock signal is generated according to the first internal clock signal which is adequately delayed or not delayed and the second internal clock signal which is adequately delayed or not delayed. Whether or not the clock of the DRAM and the internal clock signals are delayed is determined by setting select signals of the multiplexers within the north bridge by means of the BIOS, external switches or other logic circuits. Therefore, the DRAM has enough setup time at the rising edge of the work clock to correctly read the command word. Accordingly, the north bridge can correctly receive data from the DRAM and then transfer the data to the CPU or AGP.
The invention provides an apparatus capable of programmably delaying a clock of a DRAM, which is suitable for a chipset, such as a north bridge. The apparatus comprises a first delay circuit for receiving a command output clock signal to select an adequate delay time to output the command output clock signal; a first multiplexer for receiving the command output clock signal and a feedback input clock signal and then selecting one of them; a second delay circuit coupling to the output of the first multiplexer for adequately delaying the output signal of the first multiplexer; a third delay circuit, for receiving the feedback input clock signal to select an adequate delay time to output the feedback input clock signal; and a phase locked loop circuit for receiving the adequately delayed command output clock signal and the adequately delayed feedback input clock signal and outputting a bus output clock signal to the DRAM. Selection of an adequate delay of the clock of the DRAM is made by setting select signals of the multiplexers within the north bridge by means of the BIOS, external switches or other logic circuits. Therefore, the DRAM has enough setup time at the rising edge of the work clock to correctly read the command word. Accordingly, the north bridge can correctly receive the data from the DRAM and then transfer the data to the CPU or AGP.
The method according to the present invention can be applied to a chipset which comprises signals of command output clock, feedback input clock and bus input clock, wherein the bus input clock signal is used for outputting to the DRAM. Furthermore, the method comprises the steps of selecting an adequately delayed command output clock signal, selecting an adequately delayed reference clock s
Chen Chia-Hsin
Lai Jiin
Huang Jiawei
J. C. Patents
Lam David
Nelms David
VIA Technologies Inc.
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