Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-01
2008-07-01
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S147000, C711S148000, C711S141000, C711S135000, C711S138000
Reexamination Certificate
active
07395381
ABSTRACT:
A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor an invalidating snoop with respect to a physical address of a portion of a memory in a multiprocessor system from a second processor, checking whether a cache of the first processor stores a copy of data associated with the physical address, and recording an identification (ID) of the second processor if the cache of the first processor stores the copy of data associated with the physical address. Other embodiments have been claimed and described.
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
McLean-Mayo Kimberly
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