Method and an apparatus to reduce duty cycle distortion

Details Method and an apparatus to reduce duty cycle distortion Method and an apparatus to reduce duty cycle distortion

2007-01-30

2007-01-30

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S083000, C327S156000

Reexamination Certificate

active

10962929

ABSTRACT:
A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit block may comprise a positive output, a negative output and a first transistor coupled between the positive input and the positive output. The second transistor may be coupled between the negative input and the negative output of the second CML circuit block.

REFERENCES:
patent: 6411145 (2002-06-01), Kueng et al.
patent: 6466078 (2002-10-01), Stiff
patent: 6798297 (2004-09-01), Kwan et al.
patent: 6836185 (2004-12-01), Pobanz
patent: 6967514 (2005-11-01), Kizer et al.

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