Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
2007-03-13
2007-03-13
Fleming, Fritz (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S221000
Reexamination Certificate
active
10353662
ABSTRACT:
A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.
REFERENCES:
patent: 6405305 (2002-06-01), Meier et al.
Iacobovici Sorin
Nuckolls Robert
Sugumar Rabin A.
Thimmannagari Chandra M. R.
Fleming Fritz
Moll Jesse
Osha-Liang LLP
Sun Microsystems Inc.
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