Method and a device for testing electronic memory devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S741000, C714S724000

Reexamination Certificate

active

09823926

ABSTRACT:
A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.

REFERENCES:
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patent: 5566386 (1996-10-01), Kumakura et al.
patent: 5732033 (1998-03-01), Mullarkey et al.
Russ et al. ‘Non-intrusive built-in self-test for FPGA and MCM applications;’IEEE; pp. 480-485; Aug. 8-10, 1995.
NN74091034: “Circuit Diagnosis and Design Analysis System; IBM Tech. Discl. Bulletin, Jul. 1987, US, vol. 17 ISSUE: 4 1034-1036 ; Sep. 1, 1974”.
NN74091034: “Circuit Diagnosis and Design Analysis System; IBM Tech. Discl. Bulletin, Jul. 1987, US, vol. 17 Issue: 4; Sep. 1, 1974,” 3 pages.

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