Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-01-23
2007-01-23
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S741000, C714S724000
Reexamination Certificate
active
09823926
ABSTRACT:
A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.
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Russ et al. ‘Non-intrusive built-in self-test for FPGA and MCM applications;’IEEE; pp. 480-485; Aug. 8-10, 1995.
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Campardo Giovanni
Commodaro Stefano
Mongelli Patrizia
Picca Massimiliano
Bennett II Harold H.
Jorgenson Lisa K.
Lamarre Guy J.
Seed IP Law Group PLCC
STMicroelectronics S.r.l.
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