Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-02-14
2002-04-30
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S185240
Reexamination Certificate
active
06381185
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits and, more particularly, to semiconductor memories such as programmable, non-volatile memories which includes EPROMs, EEPROMs and Flash EEPROMs, for example. The present invention addresses the problem of testing a non-volatile semiconductor memory integrated in a dedicated semiconductor chip (stand alone memory), or a memory that is part of a more complex electronic system integrated in a single semiconductor chip (embedded memory).
BACKGROUND OF THE INVENTION
After their manufacture, integrated circuits are subjected to functional tests to ensure that they operate correctly and conform to the specified performance. The types of tests which have to be carried out on the integrated circuits vary based upon the type of circuit. With regard to non-volatile memories in particular, and even more particularly to electrically-programmable non-volatile memories (EPROMs, EEPROMs, Flash EEPROMs), an important check which has to be performed is that of checking their ability to retain the data programmed and thus stored in the memory. This check is necessary to be able to offer a product with a guarantee that it is reliable over time.
Typically, tests of this type are carried out on each integrated memory circuit by suitable test instruments by first programming all of the memory cells so that each cell which, as is known, comprises a MOS transistor with a modifiable threshold voltage that is brought to a high threshold-voltage state. Each cell is then individually accessed to identify the lowest of the threshold voltages of all of the cells. This value is subsequently compared with a new lowest value which is normally different and typically lower. The new lowest value is obtained by making the same measurement after the integrated memory circuit has been subjected to a thermal stress (baking) to simulate ageing of the product.
On the basis of the change in the lowest threshold voltage before and after the thermal stressing, it is possible to establish criteria on the basis of which to discard products which do not ensure the desired performance or, when there are several qualitative categories for the same product, to classify the product in the correct category on the basis of its performance characteristics.
As mentioned, the identification of the lowest threshold voltage of the memory cells before and after the device has been subjected to thermal stress provides for a measurement to be taken by accessing the individual cells, that is, by the so-called direct memory access (DMA) technique. This technique provides for each cell to be individually addressed from external the memory, and for the current absorbed by the cell as its gate voltage increases to be measured by an ammeter. This requires bypassing the cell-reading circuitry integrated in the device.
Clearly, an approach of this type is extremely slow and therefore expensive, since it lengthens the overall production time. This is true in particular for medium-capacity or high-capacity memory devices having a very large number of memory cells, such as those which are available nowadays.
SUMMARY OF THE INVENTION
In view of foregoing background, an object of the present invention is therefore to provide a method of testing an integrated circuit comprising a non-volatile memory, particularly a programmable, non-volatile memory, which does not involve the disadvantages intrinsic in current methods used.
Another object of the present invention is to provide, in particular, a method of checking the retention of the data programmed into the memory, which does not involve the disadvantages of current methods.
Yet another object of the present invention is to provide a circuit architecture for implementing these methods.
According to the present invention, a method for testing a programmable, non-volatile memory comprising a matrix of memory cells is provided. The method preferably comprises programming a plurality of the memory cells, and addressing, in succession, the programmed memory cells to identify a lowest of threshold voltage levels. The addressing for each memory location comprises:
a) applying a selection voltage that is lower than the lowest threshold voltage level to a word line of the matrix of memory cells corresponding to a memory location currently being addressed,
b) reading bits from the programmed memory cells of the memory location currently being addressed,
c) repeating step b) while progressively changing the selection voltage supplied to the word line corresponding to the memory location currently being addressed until it is detected that at least one of the bits of the memory location currently being addressed has switched from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a reading of a non-programmed memory cell, the selection voltage for which the switching is detected being the low threshold voltage level of the threshold voltages of the programmed memory cells in the memory location currently being addressed,
d) comparing the low threshold voltage level in the memory location currently being addressed as determined in step c) with a stored value corresponding to the lowest of the low threshold voltages of the memory locations previously addressed, and
e) storing the lowest threshold voltage level of the memory location currently being addressed if it is lower than a stored value.
The step b) for reading may be performed using reading circuits connected to the matrix of memory cells, and wherein step c), to detect the switching of at least one of the bits of the memory location currently being addressed, output signals from the reading circuits are supplied to a logic circuit for switching a respective output signal when at least one of the output signals of the reading circuits switches from the first logic level to the second logic level. The logic state of the output signal of the logic circuit is monitored to detect the switching.
Another aspect of the present invention is to provide an integrated circuit comprising a matrix of programmable, non-volatile memory cells, a plurality of word lines connected to the matrix of memory cells, and a plurality of reading circuits for reading, in parallel, memory cells belonging to a memory location currently being addressed.
The integrated circuit preferably includes a logic circuit having inputs for receiving outputs from the plurality of reading circuits. The logic circuit switches its own output when at least one of the outputs from the plurality of reading circuits switches from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a non-programmed memory cell.
A first externally accessible terminal is also provided, and an output circuit selectively connects an output of the logic circuit to the first externally accessible terminal for connecting to an external test device. The integrated circuit further comprises a second externally accessible terminal, and wherein the output circuit is activated by setting the integrated circuit in a checking mode by applying to the second externally accessible terminal a voltage having a value outside a range of threshold voltage values that can be applied to the second externally accessible terminal during normal operation of the matrix of memory cells.
REFERENCES:
patent: 5402370 (1995-03-01), Fazio et al.
patent: 5625591 (1997-04-01), Kato et al.
patent: 5675546 (1997-10-01), Leung
patent: 6243839 (2001-06-01), Roohparvar
patent: 6246617 (2001-06-01), Urakawa
patent: 0903753 (1999-03-01), None
Bellomo Ignazio
Camera Alessandro
Pidutti Albino
Sandri Paolo
Allen, Dyer, Doppelt, Milbra & Gilchrist, P.A.
Jorgenson Lisa K.
Phan Trong
STMicroelectronics S.r.l.
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