Metastability injector for a circuit description

Details Metastability injector for a circuit description Metastability injector for a circuit description

2007-06-07

2008-11-18

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07454728

ABSTRACT:
During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

REFERENCES:
patent: 4575664 (1986-03-01), Leslie
patent: 5465216 (1995-11-01), Rotem et al.
patent: 6175946 (2001-01-01), Ly et al.
patent: 6192505 (2001-02-01), Beer et al.
patent: 6408265 (2002-06-01), Schultz et al.
patent: 6548997 (2003-04-01), Bronfer et al.
patent: 6580773 (2003-06-01), Corvasce
patent: 6609229 (2003-08-01), Ly et al.
patent: 7082584 (2006-07-01), Lahner et al.
patent: 7089518 (2006-08-01), Bair et al.
patent: 7139988 (2006-11-01), Chard
patent: 7319729 (2008-01-01), Gundurao
patent: 2005/0069369 (2005-03-01), Gundurao et al.
patent: 2005/0097484 (2005-05-01), Sarwary et al.
patent: 2005/0268265 (2005-12-01), Ly
patent: 2005/0273735 (2005-12-01), Largelas
patent: 2006/0206846 (2006-09-01), Kowatari
Robert K. Brayton et al.; VIS: A System for Verification and Synthesis; Proceedings on Computer-Aided Verification; Jul. 1996; pp. 1-4.
Chris Ka-Kei Kwok et al.; “Using Assertion-Based Verification to Verify Clock Domain Crossing Signals”; Design & Verification Conference (DVCon) Technical Paper; Feb. 2003; DVCon; pp. 1-9.
Tim Behne; “FPGA Clock Schemes”; Embedded Systems Programming; Feb. 10, 2003; URL: http://www.embedded.com/shared/printableArticle.jhtml;jsesessionid . . . ; pp. 1-6.
Michael Crews et al.; “Practical Design for Transferring Signals Between Clock Domains”; www.edn.com; Feb. 20, 2003; pp. 65, 66, 68, 71.
Jens Renneert et al.; “Clock Domain Modeling is Essential in High Desity SOC Design”; EETIMES; Jun. 6, 2003; URL: http://eetimes.com/article/printableArticle.jhtml;jsessionid . . . ; pp. 1-20.
Edmund Clarke et al.; “Bounded Model Checking Using Satisfiability Solving”; Published in Formal Methods in System Design; vol. 19, iss. 1; Jul. 2001; Kluwer Academic Publishers; pp. 1-20.
Christoph Keran et al.; “Formal Verification in Hardware Design: A Survey”; in ACM Trans. On Design Automation of Electronic Systems; vol. 4; Apr. 1999; pp. 1-61.
William J. Dally ey al.; “Digital Systems Enineering”; Cambridge University Press; 1998; pp. 462-513.
Edmund M. Clarke, Jr. et al.; “Model Checking”; The MIT Press, Cambridge Mass.; 1999; pp. 35-49.
“VIS: A system for Verification and Synthesis”; The VIS Group, In the Proceedings of the 8th International Conference on Computer Aided Verification, pp. 428-432; Springer Lecture Notes in Computer Science, #1101; Edited by R. Alur and T Henzinger, New Brunswick, NJ, Jul. 1996; pp. 1-2.
J.R. Burch' “Symbolic Model Checking: 1020 States and beyond”; Information and Computation, vol. 98 No. 2; Jun. 1992; pp. 428-439.
Yatin Hoskote et al.' “Coverage Estimation for Symbolic Model Checking”; ACM Inc. 1999; pp. 1-6.
Jerry R. Burch et al.; “Automatic Verification of Pipeling Microprocessor Control”; Conference on Computer-Aided Verification Jun. 1994; pp. 1-17.
E.M. Clarke et al.; “Automatioc Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications”; ACM Transactions on Programming Languages and Systems; vol. 8, No. 2; Apr. 1986; pp. 224-263.
David L. Dill et al.; “Protocol Verifications as Hardware Design Aid”; Stanford University; 1992; pp. 1-4.
Donald E. Thomas et al.; “The Verilog Hardware Discription Language, Fifth Edition”; Verilog of Cadence Design Systems Inc.; 2002; pp. 195-210.
K.L. McMillan; “Symbolic Model Checking—and Approach to the State Explosion Problem”; Carnegie Mellon University 1992; pp. 1-212.
Ran Ginosar;“Fourteen Ways to Fool Your Synchronizer”; ASYNC'03; 2003; IEEE Computer Society; pp. 1-8.

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