Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-04-08
2008-04-08
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11140678
ABSTRACT:
A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.
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Author: Ran Ginosar, “Fourteen Ways to Fool Your Synchronizer”, ASYNC'03), © 2003 IEEE Computer Society, 8 pages.
Gupta Vijaya Vardhan
Kwok Ka Kei
Ly Tai An
Widdoes, Jr. Lawrence Curtis
Dimyan Magid Y.
Trellis Intellectual Property Law Group, PC
Whitmore Stacy A
Young Brian N.
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