Metallurgy for semiconductor devices

Details Metallurgy for semiconductor devices Metallurgy for semiconductor devices

2001-05-14

2002-07-30

Ho, Hoai V. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S759000

Reexamination Certificate

active

06426558

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to the manufacture of semiconductor devices and particularly to the manufacture of metallurgy for integrated circuit devices.
DESCRIPTION OF THE PRIOR ART
The manufacture of semiconductor devices requires the successful completion of several hundred discrete manufacturing steps. Although the yield for each step may be high, the cumulative yield many times is quite low. Thus, each process step becomes a critical factor in the, overall yield and ultimate cost of the semiconductor device being manufactured
BRIEF SUMMARY OF THE INVENTION
This invention relates to the formation of metallurgical interconnects for semiconductor devices and specifically is directed to the formation of contacts formed at the semiconductor surface which interface with metallurgy formed of copper-based metals. While copper has begun to displace the use of aluminum-based materials as metallurgical interconnects in semiconductor devices, copper cannot merely be substituted for aluminum. Because copper cannot be used in direct contact with a semiconductor substrate, it is necessary to provide a barrier conductor between copper and the remainder of the copper metallurgy. Typically this barrier conductor is the same refractory metal interconnect used previously with aluminum-based metallurgy, as described in more detail in U.S. Pat. No. 5,760,475. Such contacts are typically formed by a Physical Vapor Deposition (PVD) process of a layer of a refractory metal liner into a via formed in a dielectric layer, followed by a Chemical Vapor Deposition (CVD) process filling the remainder of the via with, for example, tungsten.
Because CVD processes form conformal deposited layers, via holes tend to fill in such a manner that a “seam” forms in the center of the via. These seams do not create a process yield problem when PVD aluminum metallurgy is subsequently deposited and subtractively etched. The change to copper-based metallurgy, however, has proved to be troublesome in a number of ways. Copper is preferably and most efficiently deposited by the use of an electrolytic process. We have discovered that the presence of “seams” in vias can be the source of copper plated defects which have been found to cause yield loss in semiconductor product wafers. The present invention reduces plated copper defects in the first wiring level (M
1
) caused by metal fill problem at the local interconnect (MC) level in the local interconnect(MC)/stud contact (CA)/first wiring level (M
1
) process sequence used in tungsten stud interconnect technology.
The currently practiced process sequence of stud interconnect technology is as follows:
1. Local interconnect trenches are etched into a first insulating layer deposited on top of a substrate having active devices therein.
2. The etched trenches are filled with a liner/tungsten core to make contact with some portions of the substrate devices and polished to be coplanar with the first insulating layer to form the local interconnect (MC).
3. A second insulating layer is deposited and stud contact holes etched into it.
4. The etched stud contact holes are filled with a liner/tungsten core and polished to be coplanar with the second insulating layer forming the stud contacts (CA) imbedded in the insulating layer which make contact with the local interconnect (MC) and also with additional portions of the devices, e.g. CMOS device gate electrodes.
5. The first wiring level (M
1
) is then formed by either a deposition and subtractive etch or by a damascene process (requiring a third insulating layer). This M
1
wiring level makes contact with the stud contacts (CA).
A drawback to this processes sequence is the difficulty of completely filling long trenches with tungsten, as this leads to the formation of voids in the formn of open seams in the local interconnect layer. These seams lead to similar problems in the stud contact tungsten. The seam problem is made worse by cleaning steps between the local interconnect (MC) and stud contact (CA) levels. The voids propagated into the stud contact (CA) cause plating problems when copper wiring is used at the first wiring (M
1
).
Basically, copper plating solution works its way down into the local interconnect/stud contact (CA/MC) voids and is trapped; during subsequent high temperature process steps, about 400 degrees C., the first wiring layer (M
1
) is disrupted when the trapped plating solution explodes.
This invention eliminates the problem by forming the local interconnect (MC) and stud contact (CA) as a monolithic structure. The present invention reduces the extent of the stud contact (CA) voiding by eliminating the need for the clean between local interconnect (MC) and stud contact (CA) that increases the size of the local interconnect (MC) seam. The invention accomplishes this by forming the local interconnect (MC) and stud contact (CA) monolithically. The lower portion of the combined local interconnect/stud contact (MC/CA) interconnect performs the same function as the local interconnect (MC) level, and the upper portion of the combined local interconnect/stud contact (MC/CA) interconnect performs the function of stud contact (CA).
It is an object of the invention to provide enhanced reliability and product yield by simplifying the process sequence.
It is another object to enhance the metallurgical interconnect technology for copper-based semiconductor wiring.
These and other objects will become more apparent to those skilled in the art in view of the further description of the preferred embodiments of the invention and the accompanying drawings.


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patent: 6130102 (2000-10-01), White, Jr. et al.
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patent: 6150721 (2000-11-01), Bandyopadhyay
patent: 6174803 (2001-11-01), Harvey
patent: 6316801 (2001-11-01), Amanuma

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