Metallization performance in electronic devices

Details Metallization performance in electronic devices Metallization performance in electronic devices

2008-03-04

2008-03-04

Lee, Eugene (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S767000, C257S762000, C257S773000, C257S776000, C257SE21577

Reexamination Certificate

active

07339274

ABSTRACT:
Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.

REFERENCES:
patent: 5268329 (1993-12-01), Chittipeddi et al.
patent: 5290731 (1994-03-01), Sugano et al.
patent: 5358733 (1994-10-01), Lur et al.
patent: 5798301 (1998-08-01), Lee et al.
patent: 5930669 (1999-07-01), Uzoh
patent: 6342448 (2002-01-01), Lin et al.
patent: 6380628 (2002-04-01), Miller et al.
patent: 6586334 (2003-07-01), Jiang
patent: 6614114 (2003-09-01), Gris

Affiliated with

Also associated with

Rating

Metallization performance in electronic devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Metallization performance in electronic devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metallization performance in electronic devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2804900