Metal source and drain mos transistor

Details Metal source and drain mos transistor Metal source and drain mos transistor

2002-09-19

2004-09-07

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S346000, C257S347000

Reexamination Certificate

active

06787845

ABSTRACT:

DESCRIPTION
1. Technical Field
This invention relates to a MOS (Metal-Oxide-Semiconductor) type transistor with metallic source and drain, and manufacturing processes for such a transistor.
Its applications are in the microelectronics fields, particularly for manufacturing integrated circuits with or without complementary transistors.
In particular, the invention is intended for use in applications requiring large scale integration of components, low energy consumption or high operating frequency.
2. State of Prior Art
FIG. 1
shows a diagrammatic cross section of a conventional MOS transistor at the end of an integration process for this transistor. The manufacturing process is the same for transistors with an n channel and transistors with p channels, apart from the doping steps.
The transistor in
FIG. 1
comprises a p type silicon substrate
2
if the transistor has an n channel.
Two zones
4
and
6
are formed at a distance from each other on this substrate
2
.
These zones
4
and
6
are n
+
type diffused zones forming the transistor source and drain.
As can be seen in
FIG. 1
, zones
4
and
6
are prolonged by zones
8
and
10
respectively, that are n
−
type diffused zones (less doped than zones
4
and
6
).
Zones
8
and
10
form extensions of the source and drain zones under the transistor grid which will be discussed later.
The transistor in
FIG. 1
also comprises two zones
12
and
14
that extend above zones
4
and
6
and approximately at the same level as zones
8
and
10
respectively (which are facing each other and are separated from each other only by a thin interval p type silicon).
These zones
12
and
14
are made of a metallic silicide and are self-aligned with respect to the transistor grid and with respect to the field insulation zones of this transistor, which will be discussed later.
Zones
12
and
14
form the shunt-metallisation of the transistor source and drain.
There is an electrically insulating layer
18
made of silica above the p type silicon zone
16
separating zones
8
and
10
from each other, extending also above these zones
8
and
10
and forming the insulation for the transistor grid.
There is a layer
20
made of polycrystalline silicon above layer
18
.
There is a layer
22
above this layer
20
that is made of a metallic silicide and forms a shunt-metallisation.
The transistor grid is formed from these layers
20
and
22
.
Furthermore, two electrically insulating spacers
24
and
26
, for example made of silica or silicon nitride, extend on each side of the stack formed by the layers
20
and
22
, as far as the grid insulation
18
.
The transistor shown in
FIG. 1
is electrically isolated from other identical transistors (not shown), also formed on the substrate
2
, due to LOCOS type field insulation zones
28
and
30
.
The entire structure thus obtained is covered by an insulating layer
32
made of silica glass doped with phosphorus and boron.
Two openings pass through this layer
32
on each side and open up on zones
12
and
14
respectively.
These two openings are filled with a metal by chemical vapour phase deposition and form the source and drain contacts
34
and
36
respectively.
The transistor in
FIG. 1
also comprises two metallic interconnection layers
38
and
40
that are located on the surface of layer
32
and extend contacts
34
and
36
respectively.
The grid contact is not shown in FIG.
1
.
FIG. 2
is a diagrammatic cross sectional view through another conventional MOS transistor.
This is a MOS on SOI (Silicon On Insulator) transistor that is shown at the end of its integration process.
The transistor in
FIG. 2
is different from the transistor in
FIG. 1
due to the fact that the layers
4
and
6
in it are much thinner and that these layers
4
and
6
and the silicon zone
42
between these layers are supported on a buried silicon oxide layer
44
that is itself supported on a silicon substrate
46
.
The MOS transistors described above have a number of limitations related to their electronic characteristics and their dimensions on the substrate.
One of the main limitations is due to the value of the channel access resistance. This is due mainly to the internal resistance of the source and drain regions, and also to the quality of the source-channel and drain-channel contacts.
The access resistance to the transistor channels forms a constraint that has a negative influence, particularly on the operating speed performances and the consumption of the circuits on which they are installed.
The access resistance may be reduced by increasing the doping concentration in the source and drain regions. However, if the concentration is too high, there may be electrical perforation problems and this may be harmful to the life of the transistors.
The access resistance may also be reduced by increasing the thickness of the channel and the source and drain regions. A difficulty also arises in this case in the sense that a greater thickness of these regions can cause perforation of the transistor and leakage currents between the source and the drain. A greater thickness of the source and drain regions also causes an increase in the parasite source/substrate and drain/substrate capacitances.
A shallow depth of the channel and of the source and drain regions improves the behaviour of the transistor but increases the access resistance.
Furthermore, the production of contacts such as contacts
34
and
36
that can be seen in
FIGS. 1 and 2
, depends on the alignment precision of the manufacturing tools used. This constraint tends to prevent large scale integration of transistors and a reduction in their size.
FIG. 3
shows another type of known MOS transistor.
This type of transistor comprises a grid structure
57
comparable to the grid structure in
FIGS. 1 and 2
, described above. This structure lies above a very thin channel
95
defined in a substrate
50
.
A metallic source and drain
92
,
94
can be seen on each side of the grid structure. The source and drain are self-aligned on the grid structure
57
and extend partly underneath it. The reference
58
denotes an etching and polishing stop layer separating the source from the drain.
Furthermore, the source and drain are separated from the substrate
50
by an insulating layer
84
. Extensions
88
and
90
of the insulating layer join the grid insulating layer and separate the source and drain regions
92
,
94
from the channel region
95
, respectively.
The extensions
88
and
90
are sufficiently thin to enable the passage of charge carriers, by the tunnel effect, from the source to the drain, through the channel in order to encourage the Coulomb blocking phenomenon.
The metallic nature of the source and drain, and their partial extension under the grid structure, tend to reduce the access resistance below the values of the transistors in
FIGS. 1 and 2
.
Furthermore, the self-alignment of the source and drain on the grid structure improves the compactness of the transistor and facilitates its miniaturisation.
A more detailed description of a transistor conform with
FIG. 3
is given in document (1), for which the references are given at the end of the description. Other documents illustrating prior art or the manufacturing technologies used are also referenced at the end of the description.
Presentation of the Invention
The purpose of the invention is to propose a MOS transistor with performances better than previously described transistors, and that does not depend on conduction by the tunnel effect.
Another purpose is to propose a particularly compact transistor of this type suitable for large scale integration for the manufacture of circuits.
Yet another purpose is to propose such a transistor that has a particularly low access resistance and that is particularly resistant to electrical perforation or leakage phenomena.
Another purpose of the invention is to propose process for manufacturing such a transistor.
More precisely, the purpose of the inventions is a MOS transistor comprising:
a channel region made of semico

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