Metal silicide transistor gate spaced from a semiconductor...

Details Metal silicide transistor gate spaced from a semiconductor... Metal silicide transistor gate spaced from a semiconductor...

1997-10-14

2001-07-24

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S411000, C257S344000, C257S513000

Reexamination Certificate

active

06265749

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a transistor upon a semiconductor substrate in which the gate conductor comprises cobalt silicide and the gate dielectric comprises a ceramic having a relatively high dielectric constant.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V
T
, while the transistor is in its on state. Several factors contribute to V
T
, one of which is the gate-to-substrate capacitance. The higher the gate-to-substrate capacitance, the lower the V
T
of a transistor. The value of this capacitance is dependent upon the thickness of the gate oxide, and the relative permittivity of the gate oxide. Unfortunately, the relative permittivity, or dielectric constant, &kgr;, of the gate oxide limits the amount of gate-to-substrate capacitance that can be achieved when a transistor is in operation. Permittivity, &egr;, of a material reflects the ability of the material to be polarized by an electric field. The capacitance between two layers of conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, &egr;
o
. Hence, the relative permittivity or dielectric constant of a material is defined as:
&kgr;=&egr;/&egr;
o
Since oxide (i.e., silicon dioxide) has a relatively low &kgr; of approximately 3.7 to 3.8, the minimum value of V
T
, and thus the transistor switching speed must be somewhat sacrificed in order to promote capacitive coupling between the gate conductor and the substrate.
As mentioned above, the gate-to-substrate capacitance is also affected by the thickness of the gate oxide. Conventional transistors typically include an ultra thin gate oxide to reduce the gate-to-substrate capacitance, and thereby lower V
T
. The value of the gate-to-source voltage, V
GS
, required to invert the channel underneath the gate conductor such that a drive current, I
D
, flows between the source and drain regions of the transistor is decreased. Consequently, the switching speed (from off to on and vice versa) of the logic gates of an integrated circuit employing such transistors is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Unfortunately, thin oxide films may break down when subjected to an electric field. Particularly, for a gate oxide which is less than 50 Å thick, it is probable that when V
GS
is equivalent to only 3V, electrons can pass through the gate oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that these electrons may become entrapped within the gate oxide by e.g., dangling bonds. As a result, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, V
T
may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of V
GS
, as a result of defects in the gate oxide. Such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice. Low breakdown voltages also correlate with high defect density near the surface of the substrate.
It would therefore be desirable to develop a technique for fabricating a transistor with reduced gate-to-substrate capacitance which is substantially resistant to gate dielectric breakdown. Fabrication of a relatively thin gate oxide interposed between the gate and the substrate must be avoided. A transistor with the immediately preceding advantages must also switch on and off quickly, thereby providing for high frequency operation of an integrated circuit. Further, formation of a tunneling current between the gate dielectric and the gate conductor of the resulting transistor would be less likely. The possibility of electrons becoming trapped within the gate dielectric would also be reduced. The transistor would thus be substantially resistant to threshold skews from the desired value of V
T
.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the technique hereof for fabricating a transistor in which the gate dielectric is composed of a ceramic having a relatively high dielectric constant, &kgr;. The gate-to-substrate capacitance, being directly proportional to &kgr;, is thus reduced, causing a decrease in the transistor threshold voltage, V
T
. As a result, an integrated circuit employing such transistors can more quickly transition between logic states. Further, the reduction of the gate-to-substrate capacitance can be accomplished advantageously without resorting to decreasing the gate dielectric thickness. In other words, a thicker gate dielectric can be used to achieve the same V
T
as compared to using a gate dielectric composed of oxide. Therefore, the probability that the gate dielectric will breakdown is significantly reduced. In this manner, problems such as current passing through the gate dielectric and electron entrapment within the gate dielectric are less likely to be encountered.
The present invention further contemplates the formation of a gate conductor comprising metal silicide, preferably cobalt silicide, above the ceramic gate dielectric. The gate conductor is formed by depositing a layer of polysilicon across the gate dielectric and then cobalt across the polysilicon layer. The semiconductor topography is subjected to a one-step anneal to promote a reaction between cobalt atoms and silicon atoms within the polysilicon layer such that cobalt silicide forms. Preferably, the amount of polysilicon that is deposited is commensurate to that which is consumed. The resulting cobalt silicide gate conductor exhibits a relatively low sheet resistance which is lower than that of the conventional doped polysilicon gate conductor. Using a low resistivity cobalt silicide gate conductor provides for a lower V
T
value. Thus, the combination of a relatively high &kgr; gate dielectric with a relatively low resistivity metal silicide gate conductor can be used to form faster operating integrated circuits.
According to one embodiment of the present invention, a semiconductor substrate is provided. The substrate may be placed in one chamber of a multi-chamber system to remove any residual oxide from the substrate. The oxide removal process first involves pumping down the chamber to a relatively low pressure, thereby forming a vacuum within the chamber. A plasma etch process is then performed to remove the oxide using an NF
3
and N
2
entrained gas. A robotics arm of the multi-chamber

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