Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-11-12
2004-03-16
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
Reexamination Certificate
active
06706640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to plasma etch methods for forming patterned layers within microelectronic products. More particularly, the present invention relates to metal silicide etch resistant plasma etch methods for forming patterned layers within microelectronic products.
2. Description of the Related Art
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common within the microelectronic product fabrication art to employ metal silicide layers as contact layers for microelectronic conductor layers and microelectronic conductor structures. Metal silicide layers are desirable as contact layers insofar as metal silicide layers generally provide low contact resistance contact layers.
While metal silicide layers are thus desirable in the microelectronic product fabrication art and often essential in the microelectronic product fabrication art, metal silicide layers are nonetheless not entirely without problems. In that regard, it is often difficult to maintain the physical and electrical integrity of metal silicide layers when fabricating microelectronic products.
It is thus desirable to provide methods for maintaining the integrity of metal silicide layers formed therein when fabricating microelectronic products.
It is towards the foregoing object that the present invention is directed.
Various methods for fabricating microelectronic products having formed therein metal silicide layers have been disclosed within the microelectronic product fabrication art.
Included but not limiting among the methods are methods disclosed within: (1) Autryve, in U.S. Pat. No. 5,935,877 (a plasma etch method for forming a via reaching a titanium silicide layer absent etching the titanium silicide layer); and (2) Thei et al., in U.S. Pat. No. 6,265,271 (a method which integrates a salicide metal silicide layer within the context of a borderless contact structure). The teachings of each of the foregoing references are incorporated herein fully by reference.
Desirable are additional methods for fabricating microelectronic products having formed therein metal silicide layers while maintaining the integrity of the metal silicide layers.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the invention is to provide a method for fabricating a microelectronic product having formed therein a metal silicide layer.
A second object of the invention is to provide a method in accord with the first object of the invention, wherein the integrity of the metal silicide layer is maintained.
In accord with the objects of the invention, the present invention provides a method for fabricating a microelectronic product.
To practice the method of the invention, there is first provided a substrate having formed thereover a metal silicide layer. There is then formed upon the metal silicide layer an etch stop layer. There is then formed upon the etch stop layer a dielectric layer. There is then etched, while employing a first etch method, the dielectric layer to form a patterned dielectric layer which exposes the etch stop layer. Finally, there is then etched, while employing a second plasma etch method, the etch stop layer to form a patterned etch stop layer which exposes the metal silicide layer. Within the invention, the second plasma etch method employs an etchant gas composition comprising a fluorine containing gas and a nitrogen containing gas, without an oxygen containing gas or a carbon and oxygen containing gas.
Within the invention, the etchant gas composition employed within the second plasma etch method preferably may also comprise a carrier gas, such as helium or argon.
Within the invention, a patterned photoresist layer employed within the first etch method as an etch mask layer is stripped prior to etching the etch stop layer to form the patterned etch stop layer while employing the second plasma etch method.
The invention provides a method for fabricating a microelectronic product having formed therein a metal silicide layer, wherein the integrity of the metal silicide layer is maintained.
The invention realizes the foregoing object within the context of etching an etch stop layer to reach a metal silicide layer formed thereunder by employing a plasma etch method employing an etchant gas composition comprising a fluorine containing gas and a nitrogen containing gas without an oxygen containing gas or a carbon and oxygen containing gas. In particular, the absence of a carbon and oxygen containing gas provides for enhanced selectivity for etching the etch stop layer with respect to the metal silicide layer, since carbon and oxygen containing gases (such as carbon monoxide) readily form volatile compounds (such as volatile metal carbonyl compounds) with metals from which are formed metal silicide layers.
REFERENCES:
patent: 5269879 (1993-12-01), Rhoades et al.
patent: 5935877 (1999-08-01), Autryve
patent: 6117786 (2000-09-01), Khajehnouri et al.
patent: 6265271 (2001-07-01), Thei et al.
Hsu Ju-Wang
Hsu Peng-Fu
Tao Hun-Jan
Tsai Ming-Huan
Taiwan Semiconductor Manufacturing Co. Ltd
Thompson Craig
Tung & Associates
LandOfFree
Metal silicide etch resistant plasma etch method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Metal silicide etch resistant plasma etch method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metal silicide etch resistant plasma etch method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3209613