Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2000-03-22
2002-11-12
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S288000, C257S402000, C438S289000
Reexamination Certificate
active
06479846
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor devices, and specifically, to a metal oxide semiconductor field effect transistor (MOSFET) having a relatively high doped region in the channel for improved linearity.
BACKGROUND OF THE INVENTION
Linearity in radio frequency (RF)/microwave power amplifiers is an important characteristic in the design of these devices. Poor linearity in power amplifiers can have many adverse effects. For instance, poor linearity can result in harmonic, intermodulation, and signal compression distortions, to name a few. Thus, designers of power amplifiers continue to develop new techniques for improving the linear characteristic of power amplifiers.
Traditionally, two types of field effect transistors have been used for RF/microwave power amplification. These are the metal-oxide semiconductor field effect transistor (MOSFET) and the gallium-arsenide field effect transistor (GaAs FET). MOSFETs are desirable because their manufacturing process is less complex and inexpensive. However, they have poorer linear characteristics. GaAs FETs, on the other hand, are more frequently employed for RF/microwave power amplification applications due to their improved linearity characteristic over MOSFETs. However, their manufacturing process is more complex and expensive.
FIG. 1A
illustrates a side sectional view of a traditional MOSFET
100
used to illustrate their non-linearity characteristic. For linearity purpose, the only parameter that should vary the drain current (Id) is the gate voltage (+Vg). If other parameters vary the drain current, a non-linear drain current (Id) can result in response to an input voltage (+Vg) at the gate. One such parameter is the drain voltage (+Vd). If the drain voltage (+Vd) changes the drain current, then a non-linear output results in response to an input voltage (+Vg) at the gate. This characteristic of the traditional MOSFET
100
will be explained in more detail with reference to FIG.
1
A.
As shown in
FIG. 1A
, the traditional MOSFET
100
comprises a semiconductor substrate
102
having a relatively light p-type doping (p−), a drain region
104
having a relatively high n-doped region (n+)
104
a
and a relatively light n-doped region (n−)
104
b
, and a source region
106
having a relatively high n-doped region (n+)
106
. The source region
106
may include a relatively high p-doped region (p+)
110
which provides a body contact to the p-channel for grounding and other purposes. A current conduction channel is
112
is formed between the drain
104
and source
106
regions. The traditional MOSFET
100
further includes a gate electrode
114
deposited on the p-channel that on the substrate
102
.
As typical of MOSFETs, a depletion region is formed within the channel
112
which affects the current conduction characteristic of the channel
112
. Assuming the gate voltage (+Vg) applied to the gate electrode
114
remains constant, the depletion region within the channel varies as a function of the drain voltage (+Vd). The undepleted region within the channel is defined in
FIG. 1A
as the length under gate (Lug). As
FIG. 1A
illustrates, holding the gate voltage (+Vg) constant and adjusting the drain voltage to Vd
1
, the Lug
1
is relatively small (corresponding to a smaller series resistance) which results in a relatively larger drain current. If the drain voltage is changed to Vd
2
with the gate voltage (+Vg) held constant, the Lug
2
is relatively large (corresponding to a larger series resistance), which results in a relatively smaller drain current. Thus, this shows that the traditional MOSFET
100
behaves in a non-linear fashion since the drain voltage (+Vd) can substantially vary the depletion region.
FIG. 1B
illustrates a schematic diagram of an equivalent circuit for the traditional MOSFET
100
. From an equivalent circuit standpoint, the MOSFET
100
comprises a drain-to-gate capacitance Cdg that varies as a function of the gate voltage (Vdg), a gate-to-source capacitance Cgs which is substantially constant, and a drain-to-source capacitance Cds which is also substantially constant. The equivalent circuit MOSFET
100
further includes a current source
120
representing the drain current and a resistance of the channel (termed herein as resistance-under-gate (Rug)). It is noted that because of the non-linearity of the traditional MOSFET
100
as explained above, the channel resistance Rug varies as a function of the drain voltage (Vd), the gate-to-source voltage (Vgs), and the temperature T. Thus, for the sake of linearity, it would be preferable for a MOSFET
100
to vary substantially only with variations in the gate-to-source voltage (Vgs) when the device is in saturation.
FIG. 1C
illustrates the drain current (Id) versus drain voltage (Vd) for the traditional MOSFET
100
. As the curves illustrates, when the traditional MOSFET
100
reaches the saturation region, there is still a positive slope of the drain current (Id) with increases in the drain voltage (Vd). Because of this, the traditional MOSFET
100
does not have the linearity that many power amplifier designers desire.
Thus, there is a need for a MOSFET type semiconductor device that provides improved linearity over traditional MOSFET devices.
SUMMARY OF THE INVENTION
A general concept of the invention is to include a relatively higher doped region (of the same type dopant as the channel) to reduce the change in the depletion region within the channel with changes in the drain voltage (Vd). As previously discussed, changes in the drain current (Id) with changes in the drain voltage (Vd) is a cause of non-linearity for traditional MOSFET. Because of the additional higher doped region provided in the channel, the depletion region within the higher doped region changes less with changes in the drain voltage (Vd). The higher doped region is situated at the top of the channel, where most of the drain current flows. Thus, the higher doped region contains the drain-to-source current. Any performance dependent depletion modulation in the path of the current will be minimally effected since the change in channel resistance will be minimized. This results in a reduced sensitivity of the drain current (Id) to the drain voltage (Vd). Since the drain current is less susceptible to changes with changes in drain voltage (Vd), a more linear device results. The MOSFET device may be incorporated as an individual device or in an integrated circuit.
A more specific exemplary embodiment includes a field effect transistor, comprising a substrate, a drain region formed within the substrate, a source region formed within the substrate, a current conduction channel formed within the substrate between the drain and source regions, a gate electrode formed over an oxide which is on the substrate above the channel, and a doped region formed within the channel to reduce an effect of a drain-to-source voltage has on a drain current when the field effect transistor is in saturation.
Another aspect of the invention is an amplifier that uses the field effect transistor of the invention. Specifically, the amplifier comprises a field effect transistor having a doped region formed within a channel to reduce an effect of a drain-to-source voltage has on a drain current when the field effect transistor is in saturation, an input impedance matching circuit coupled to a gate terminal of the field effect transistor, and an output impedance matching circuit coupled to a drain terminal of the field effect transistor.
A further aspect of the invention includes a field effect transistor comprising a substrate, a drain region formed within the substrate, a source region formed within the substrate, a doped channel formed within the substrate between the drain and source regions; a gate electrode formed over the substrate above the channel, and a doped region formed within the doped channel, wherein a dopant concentration of the doped region is greater than a dopant concentration of t
Blakely , Sokoloff, Taylor & Zafman LLP
Chaudhuri Olik
Nguyen Dilinh
Ophir RF, Inc.
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