Metal oxide semiconductor device with self-aligned groove channe

Details Metal oxide semiconductor device with self-aligned groove channe Metal oxide semiconductor device with self-aligned groove channe

1996-11-14

1997-09-09

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257332, 257365, H01L 2941

Patent

active

056659903

ABSTRACT:
A metal oxide semiconductor device with a self-aligned groove channel structure is disclosed comprising a substrate in which a first channel region of a first conductivity type and source and drain regions of a second conductivity type are formed, a first gate insulating layer formed on the first channel region, and a first gate electrode formed on the gate insulating layer, a second gate electrode having a self-aligned groove structure formed at both sides of the first gate electrode; a second gate insulating layer formed between the substrate and the second gate insulating layer; and a non-planar second channel region of the first conductivity type formed under the second gate insulating layer and doped with a different concentration of an impurity from the first channel region. The groove structure prevents an electric field produced in the vicinity of a drain from penetrating into the channel region to lessen a short channel effect. The length of an effective channel is increased by the groove structure, and also a junction depth of source/drain regions can be further increased by a depth of the groove in comparison with the conventional MOS device. The source/drain resistance is lowered, and reliability is increased due to lessening the effect of a junction spike of a metallization and/or an electro-migration.

REFERENCES:
patent: 4167745 (1979-09-01), Ishibashi et al.
patent: 5021846 (1991-06-01), Ueno
patent: 5082795 (1992-01-01), Temple
patent: 5422505 (1995-06-01), Shirai
patent: 5510648 (1996-04-01), Davies et al.

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