Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-29
2003-03-04
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S332000, C257S333000, C257S334000
Reexamination Certificate
active
06528847
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to metal oxide semiconductor (MOS) devices, more specifically arrangements for forming submicron MOS devices having minimal junction depths and elevated source/drain regions.
2. Background Art
Metal oxide semiconductor devices are being manufactured at smaller sizes in order to increase density of integrated circuits on a semiconductor chip. However, additional manufacturing problems are encountered as MOS devices are scaled to smaller sizes, since a shallower source/drain junction is needed. The term “source/drain junction” herein is intended to include light doped drain (LDD) or source/drain extensions.
As junctions become shallower on the order of 0.1 microns, any further reduction in size to the channel length of the device is limited by the dimension of the polysilicon (“poly”) gate and lateral diffusion. In particular, both sides of the poly gate self align with the edges of the source and drain regions, respectively. Lateral diffusion occurs under the poly gate, reducing the channel length relative to the poly gate length. Hence, the difference in length between the channel length and the poly gate depends on the lateral diffusion of the source and drain junctions.
Lateral diffusion is a function of junction depth, where lateral diffusion increases as the depth of the source and drain junctions increase. Hence, there is a desirability to minimize the lateral diffusion from the source and drain regions by scaling the junction depth when attempting to scale the polysilicon gate length.
However, reducing the junction depth in an attempt to reduce the channel length results in a higher source/drain resistance that degrades the current driving capability of the MOS device.
In addition, minimizing the depth of the source/drain junction causes additional difficulties when attempting to grow silicide at the source/drain regions. In particular, formation of silicide consumes silicon at the source/drain regions. The consumption of silicon at the source/drain regions results in a higher junction leakage that may result in spiking. The junction leakage may even short the junction and cause functional failure.
Elevated source/drain regions have been developed by growing epitaxial silicon at the source/drain regions. For example, a standard gate electrode is formed on a flat surface of a silicon substrate. Spacers are added to the gate electrode, and silicon is selectively grown over the source/drain regions to a depth of about 200-400 nm to form a stacked-source-drain (SSD) MOSFET having elevated source/drain regions. However, such SSD MOS devices still suffer from the disadvantage that lateral diffusion from the elevated source/drain regions may still affect the channel length. In addition, the epitaxial growth of silicon is not a well-controlled process. Hence, the epitaxial growth process may introduce defects. For example, the epitaxial growth process has a lateral growth problem where the grown silicon, upon reaching the level of the gate, may grow laterally and risk a short across the gate. This lateral growth becomes substantial as the MOS device is scaled to smaller dimensions. In addition, epitaxial growth suffers from the problem of comer faceting, where the interface between the epi-silicon and the sidewall of the gate is not flat, but is at an angle, resulting in defects.
SUMMARY OF THE INVENTION
There is a need for an arrangement for scaling a metal oxide semiconductor device in a manner that minimizes the reduction of source/drain junction depths and that minimizes the reduction in the channel length.
There is also a need for a MOS device that can be scaled to a reduced size without a substantial increase in the source/drain resistance.
There is also a need for an arrangement for scaling down a device without scaling down the junction depth by a corresponding amount. In other words, there is a need for an arrangement for decoupling the shallow junction requirement from channel length scaling.
These and other needs are attained by the present invention, where a MOS device has a contoured channel region that enables a scaled MOS device to have elevated source/drain regions and a substantially longer channel length, without the adverse effects of lateral diffusion.
According to one aspect of the present invention, a method of forming a metal oxide semiconductor (MOS) device comprises forming a nitride mask pattern overlying a silicon substrate, forming a locally-oxidized silicon (LOCOS) structure by oxidizing the silicon substrate at an exposed region in the nitride mask, implanting the LOCOS structure with a first impurity to form a contoured channel region having a substantially flat surface and contoured edges, and implanting portions of the silicon substrate at each end of the contoured channel region with a second impurity to form source and drain regions extending to a depth less than or equal to the substantially flat surface of the contoured channel region. The formation of the LOCOS structure and the implantation with the first impurity enables formation of a contoured channel region that extends into the substrate to a depth greater than the junctions forming the source and drain regions. The contoured channel region is not subject to the effects of lateral diffusion due to its geometry and depth relative to the source/drain regions. Hence, the requirement of a shallow junction is eliminated when scaling (i.e., reducing) the channel length.
Formation of the contoured channel region also enables a non-uniform doping profile to be established in the contoured channel region, where a higher-doped region corresponding to the substantially flat surface provides good turn-off characteristics of the MOS device. The non-uniform doping profile can also include lighter-doped regions at each of the contoured edges that interface with the respective source and drain regions. The lighter-doped regions interfacing with the source and drain regions provide better MOS device performance, for example by improving carrier mobilities and thus current driving capability, minimizing peak electrical field and hot carrier injection, improving drain induced barrier lowering (or short channel effects), and improving junction breakdown. In addition, the contoured channel region can be formed to a predetermined depth within the silicon substrate based on a length of the channel region at a predetermined power supply voltage for the MOS device. Hence, the substantially flat surface of the contoured channel can be formed below the source and drain regions to a depth based on the predetermined power supply voltage (e.g., the voltage bias).
Another aspect of the present invention provides a MOS device, comprising a silicon substrate, source and drain regions, each containing a first impurity implanted into the silicon substrate and having a predetermined junction depth relative to a surface of the silicon substrate, and a gate region. The gate region has a contoured channel region and a polysilicon gate overlying the contoured channel region. The contoured channel region has a substantially flat surface, lower than or equal to the predetermined junction depth, and contoured edges interfacing with the source and drain regions, respectively. The contoured channel region enables formation of a channel region having a non-uniform doping profile, where the substantially flat surface includes a higher doped region to optimize MOS device operating characteristics including short channel effects (SCE), whereas the contoured edges interfacing with the source and drain regions can have lighter-doped regions that provide a more uniform electric field. The more uniform electric field density improves the junction breakdown, and alleviates reverse short channel effect (RSCE), and hot carrier injection reliability problems. The lighter-doped regions also enhance the carrier mobility for better device performance. The depth of the substantially flat surfaces relative to the source and drain regions also ensures that the contoured
Advanced Micro Devices , Inc.
Thomas Tom
Tran Thien F
LandOfFree
Metal oxide semiconductor device having contoured channel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Metal oxide semiconductor device having contoured channel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metal oxide semiconductor device having contoured channel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3004943