Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-07-20
2001-10-23
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000, C257S763000, C257S764000, C257S767000, C257S768000, C257S770000
Reexamination Certificate
active
06307266
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a metal-line structure in an integrated circuit (IC) and a method of fabricating the same, which can help prevent the occurrence of extrusions along the sidewalls of the respective metal lines.
2. Description of Related Art
In VLSI (very large-scale integration) semiconductor devices, MOS (metal-oxide semiconductor) transistors are interconnected with each other and various other devices via a plurality of conductive layers called metal lines. These metal lines should be adequately isolated from each other so as to prevent short-circuits therebetween. As the level of integration rises, the isolation between the metal lines becomes very critical since these metal lines are made smaller and closer to each other. Therefore, any cracks in the dielectric layers used to isolate the metal lines from each other can cause bridging between neighboring metal lines. A conventional metal-line structure is illustratively depicted in the following with reference to
FIGS. 1A-1D
.
FIG. 1A
shows a metal-line structure constructed on a semiconductor substrate
10
, which is already formed with a plurality of MOS transistors (not shown) thereon. Next, a dielectric layer
12
is formed over the substrate
10
. After this, a barrier layer
14
is formed over the dielectric layer
12
prior to the forming of a metallization layer
16
. This barrier layer
14
can be formed from titanium nitride (TiN), titanium (Ti), tungsten nitride (WN), or the alloy of titanium and tungsten (Ti/W). This barrier layer
14
serves to prevent the occurrence of spiking between the metallization layer
16
and the substrate
10
.
The metallization layer
16
is preferably formed from aluminum. Since the metallization layer
16
has a high reflectivity to light, which can adversely affect the definition of the pattern transfer in the subsequent photolithographic process, an ARC (anti-reflective coating)
18
is coated over the entire top surface of the metallization layer
16
to eliminate this problem. The ARC
18
can be formed from any non-reflective material, but is preferably made from the same material used to form the barrier layer
14
so that the process can be carried out in a more cost-effective way.
In this case, the barrier layer
14
, the metallization layer
16
, and the ARC
18
in combination are customarily referred to as a sandwich structure (from the fact that the metallization layer
16
is sandwiched by two layers of the same material).
As
FIG. 1B
illustrates, a plurality of photoresist layers
30
are then formed at selected locations over the wafer through a photolithographic and etching process. More specifically, these photoresist layers
30
are formed at those locations where a plurality of metal lines for the IC device are to be formed.
FIG. 1C
further illustrates the subsequent step, in which an anisotropic dry etching process is performed on the wafer with the photoresist layers
30
serving as mask until the top surface of the dielectric layer
12
is exposed. Through this process, those parts of the ARC
18
, the metallization layer
16
, and the barrier layer
14
that are not covered by the photoresist layers
30
are entirely removed (the remaining parts thereof are herein and hereinafter designated instead by the reference numerals
18
a
,
16
a
,
14
a
for distinguishing purpose).
FIG. 1D
shows the subsequent step, in which the photoresist layers
30
are entirely removed. After this, the combination of each metallization layer
16
a
, the underlying barrier layer
14
a
, and the overlying ARC
18
a
constitute one metal line (as collectively designated by the reference numeral
32
). This concludes the fabrication of the metal-line structure over the dielectric layer
12
.
In the case of
FIG. 1D
, for example, two metal lines are illustrated for the purpose of demonstration. This metal-line structure serves as metal interconnects in the IC device. Customarily, a second dielectric layer called a passivation layer (not shown) will be formed over the metal-line structure for the purpose of protecting the metal-line structure against corrosion and metal shortage. All the subsequent steps to complete the fabrication of the IC device are conventional processes and not within the spirit and scope of the invention, so description thereof will not be further detailed.
In the foregoing metal-line structure, the forming of the barrier layer
14
a
over the metallization layer
16
a
has the benefit of reducing the surface reflectivity of the metallization layer
16
a
that would otherwise affect the definition of the pattern transfer in the subsequent photolithograpliic process.
Moreover, it can help prevent the undesired occurrence of dielectric cracks and interconnect bridges in the dielectric layer
12
due to the occurrence of hillocks in the upward direction. Such hillocks result from stress caused by the expansion of the metallization layer
16
a
when the structure is subjected to heat treatment in the subsequent processes.
One drawback to the foregoing metal-line structure, however, is that the sidewalls thereof are in direct contact with dielectric, which would easily cause the occurrence of extrusions along the sidewalls of the metal lines
32
after the wafer has been subjected to a series of heat-treatment processes, such as the heat treatments used for the deposition of the dielectric layer, the forming of an alloy metallization layer, and the forming of the passivation layer.
In a high integration IC device, the forming of these extrusions easily causes cracks to occur in the dielectric layer between two neighboring metal lines, thus resulting in an undesired bridging effect (i.e., a short-circuit effect) between two neighboring metal lines. The resultant IC device may thus be unreliable in operation.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a metal-line structure and a method of fabricating the same in an IC device, which can help prevent the occurrence of extrusions along the sidewalls of the metal lines, thus allowing the resultant IC device to be more reliable in operation.
It is another objective of the present invention to provide a metal-line structure and a method of fabricating the same in an IC device, which can help reduce the manufacturing cost of the IC device.
In accordance with the foregoing and other objectives of the present invention, an improved metal-line structure and a method of fabricating the same are provided.
The metal-line structure of the invention includes a barrier layer, a metallization layer, an ARC (anti-reflective coating) and a spacer structure.
The method of the invention for fabricating a metal-line structure includes the following steps. A barrier layer is formed over the dielectric layer. A metallization layer is formed over the barrier layer. An ARC is formed over the metallization layer. Selected portions of the barrier layer, the metallization layer, and the ARC are removed to form a plurality of metal lines. A spacer structure is formed over all the exposed sidewalls of each of the metal lines.
It is a characteristic part of the invention that the forming of the blanket layer can help prevent the occurrence of extrusions along the sidewalls of the metal lines after the wafer has been subjected to a series of heat-treatment processes. As a result, the undesired formation of dielectric cracks and bridging between neighboring metal lines can be prevented.
REFERENCES:
patent: 4810332 (1989-03-01), Pan
patent: 6030896 (2000-02-01), Brown
patent: 6060382 (2000-09-01), Lee
patent: 6074943 (2000-06-01), Brennan et al.
patent: 6130154 (2000-10-01), Yokoyama et al.
patent: 6133619 (2000-10-01), Sahota et al.
patent: 6140238 (2000-10-01), Kitch
Huang Jiawei
J. C. Patents
Jr. Carl Whitehead
Thomas Toniae M.
Winbond Electronics Corp.
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