Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects
Reexamination Certificate
1999-09-23
2001-06-05
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
C257S775000
Reexamination Certificate
active
06242795
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a metal line structure and its method of manufacture. More particularly, the present invention relates to a metal line structure having slanted edges on two sides for enhancing step coverage in a subsequent deposition process.
2. Description of Related Art
For most very large scale integrated (VLSI) circuits, when fabrication of the MOS transistors is nearly complete, metal layers have to be formed over the substrate to connect various transistors or other device units. The metal layers that connect various transistors or other devices are known as “metal lines”. Following the recent increase in the level of integration for VLSI circuits, the respective distances between different devices have become increasingly smaller. Hence, the density of the metal lines will correspondingly increase. Furthermore, since these metal lines actually serve as conducting wires, they must be disposed over, for example, a multiple of insulating field oxide layers in a three-dimensional way in order to link up the various devices in different locations.
FIGS. 1A and 1B
are two cross-sectional views showing the progression of manufacturing steps in producing a conventional metal line structure. First, as shown in
FIG. 1A
, on a semiconductor substrate
10
that has a transistor already formed thereon, metal is deposited to form a metallic layer
12
. The metal can be deposited using a sputtering method. In general, a thin layer of anti-reflective coating (ARC) will also be coated on top of the metallic layer
12
. Thereafter, photolithographic and etching processes are carried out to create a pattern in the metallic layer
12
. The method is to form a photoresist layer over the metallic layer
12
, and then patterning the photoresist layer. Next, using the photoresist layer as a mask, anisotropic dry etching is performed to etch away portions of the metallic layer
12
forming an opening
16
that exposes the substrate
10
. Thus, a metal line structure is complete, and it is not difficult to see that the sidewalls of these metal lines
12
are nearly vertical.
Next, as shown in
FIG. 1B
, a chemical vapor deposition (CVD) method is used to deposit a dielectric layer
18
over the metal lines
12
, and to fill the opening
16
as well. Because the sidewalls
17
of the metal lines
12
are nearly vertical, the deposited dielectric layer
18
will generally form an overhang at the upper corner of the metal lines
12
. This is due to poor step coverage by the deposited dielectric material. The overhang is actually a thick formation of the dielectric layer
18
at the upper corner locations. When the overhangs on each upper corner of the metal lines meet, a void
19
will be formed in the opening
16
. A void in the dielectric layer
18
will eventually affect the stability of the connected devices.
Since the current trend in semiconductor manufacturing is towards device miniaturization, spacing between metal lines
12
is going to be smaller. Therefore, the step coverage ability for the deposited dielectric material diminishes, and overhangs and voids increase in number.
In light of the foregoing, there is a need in the art to provide a better metal line structure and method of manufacture.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to provide a metal line structure and its method of manufacture that can increase the step coverage of deposited material during subsequent deposition over the metal lines.
To achieve these and other advantages in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a metal line structure. The method comprises the steps of providing a semiconductor substrate, and then sequentially forming a metallic layer and an insulating layer over the substrate. Next, photolithographic and etching processes are performed to create a pattern on the insulating layer exposing portions of the metallic layer and forming insulating lines. Then, spacers are formed on the sidewalls of the insulating lines. Thereafter, the metal layer is etched using the insulating lines and the spacers as masks, and the substrate as an etching stop layer. The metal etching also removes the insulating lines. Thus, the top surface of the metallic layer is exposed and the metal line structure that has the characteristic sloping sidewalls of this invention is formed. These outward sloping sidewalls of the metal lines form an angle with the semiconductor substrate, and can provide good step coverage for a subsequently deposited layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5668410 (1997-09-01), Yamamoto
patent: 5693983 (1997-12-01), Yamamoto
Potter Roy
Rabin & Champagne, P.C.
Winbond Electronics Corp.
LandOfFree
Metal line structure and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Metal line structure and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metal line structure and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2518510