Metal line stacking structure in semiconductor device and...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S774000, C257S763000, C257S764000, C257S767000, C257S773000, C257SE23160

Reexamination Certificate

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07141880

ABSTRACT:
The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.

REFERENCES:
patent: 5563099 (1996-10-01), Grass
patent: 5990011 (1999-11-01), McTeer
patent: 6204179 (2001-03-01), McTeer
patent: 6218733 (2001-04-01), Fiordalice et al.
patent: 6433433 (2002-08-01), Sengupta
patent: 6747354 (2004-06-01), Kim et al.
patent: 2002/0109235 (2002-08-01), Leiphart

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