Metal line having an increased resistance to...

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis

Reexamination Certificate

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C257S687000

Reexamination Certificate

active

10813223

ABSTRACT:
During the formation of a metallization layer of a semiconductor device, a cap layer is formed above a metal line and subsequently an implantation process is performed so as to modify the metal in the vicinity of the interface between the cap layer and the metal line. Consequently, an improved behavior in view of electromigration of the metal line may be obtained, thereby increasing device reliability.

REFERENCES:
patent: 6023100 (2000-02-01), Tao et al.
patent: WO 01/08213 (2001-02-01), None
patent: WO 01/97283 (2001-12-01), None

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