Metal layer assignment

Details Metal layer assignment Metal layer assignment

1998-07-16

2001-01-30

Lintz, Paul R. (Department: 2768)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06182272

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns integrated circuits (ICs) and IC design, and particularly relates to the assignment of specific metal layers to electrical connection (or wire) segments during integrated circuit design.
2. Description of the Related Art
FIG. 1
provides a simplified cross-sectional view of an integrated circuit chip (or die)
50
, which includes a semiconductor layer
60
, four metal layers
51
to
54
, electrically insulating layers
57
, and passivation layer
58
. Semiconductor layer
60
, which is typically polysilicon, is used for forming the transistors and other electronic devices and also may be used for routing some of the electrical connections between these electronic devices. However, wire routing occupies space on the semiconductor layer
60
which otherwise could be used for the electronic devices. As a result, ordinarily only the shorter electrical connections are formed on semiconductor layer
60
. For the remainder of the connections, metal layers
51
to
54
are provided.
Metal layers
51
to
54
may be formed from any of a variety of materials including aluminum, copper or an electrically conductive alloy. To simplify the routing process, routing typically is performed using mainly horizontal and vertical electrical connection (or wire) segments. Moreover, to permit such routing to be performed in an orderly manner, each metal layer typically is designated as either a horizontal metal layer or a vertical metal layer. Horizontal metal layers are used primarily for horizontal wire segments and vertical metal layers are used primarily for vertical wire segments. Thus, integrated circuit chip
50
typically will have two of its metal layers designated as vertical layers (e.g., layers
51
and
53
) and two of its metal layers designated as horizontal layers (e.g., layers
52
and
54
). Ordinarily, horizontal and vertical metal layers are alternated so as to facilitate horizontal-to-vertical transitions. It is also common to number the metal layers in ascending order starting with the metal layer closest to the semiconductor layer. Thus, metal layers
51
to
54
would be referred to as M
1
to M
4
, respectively. This designation is used herein.
Between each pair of adjacent metal layers and between metal layer
51
and semiconductor layer
60
is an electrically insulating layer
57
, which typically is formed as an oxide film. Electrical connections between metal layers are made using interlayer holes called vias, while direct contacts can be made between semiconductor layer
60
and metal layer
51
.
Passivation layer
58
functions to prevent the deterioration of the electrical properties of the die caused by water, ions and other external contaminants. Typically, passivation layer
58
is made of a scratch-resistant material such as silicon nitride and/or silicon dioxide.
As indicated above, current integrated circuits frequently include four metal layers. Moreover, the number of metal layers utilized has been increasing over the past few years, and it is expected that this trend will continue. However, in order to utilize such multiple metal layers, it is necessary to assign each wire segment to a specific metal layer. Unfortunately, until now, no systematic and efficient technique for assigning wire segments to specific metal layers has been proposed.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing problem by determining a penalty for a vertex where two connection segments connect with each other and assigning routing layers based on that penalty.
Thus, in one aspect the invention is directed to assigning routing layers to connection segments in integrated circuit design. A routing description that includes connection segments and a vertex where at least two of the connection segments connect to each other is obtained. A penalty is determined for the vertex based on a potential layer assignment combination for the connection segments that connect at the vertex, and routing layers are assigned to the connection segments based on the determined penalty.
In another aspect, the invention is directed to assigning routing layers connection segments in integrated circuit design. A routing description that includes connection segments and a vertex where at least two of the plural connection segments connect to each other is obtained. Penalties are determined for each of plural vertices, one penalty for each potential layer assignment combination for the connection segments that connect at the vertex. Routing layers are then assigned to the connection segments based on the determined penalties.
By virtue of the foregoing arrangements, the present invention can often provide a systematic and efficient technique for assigning wire segments to metal layer resources. In more particularized aspects of the invention graphical structures are provided which can often greatly facilitate metal layer assignment.
In other particularized aspects of the invention, various metal layer assignment combinations are evaluated using a dynamic programming technique. By providing a technique for utilizing dynamic programming when assigning metal layers, the present invention frequently can provide optimal solutions based on specified constraints in a relatively short time period. Such constraints may include, for example, minimization of the amount of metal layer area occupied by vias.
The foregoing summary is intended merely to provide a brief description of the general nature of the invention. A more complete understanding of the invention can be obtained by referring to the claims and the following detailed description of the preferred embodiments in connection with the accompanying figures.


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