Metal interconnection read only memory cell

Details Metal interconnection read only memory cell Metal interconnection read only memory cell

2001-07-30

2003-07-15

Nelms, David (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06594812

ABSTRACT:

TECHNICAL FIELD
The present invention relates to read only memory (ROM) cells. The present invention also relates to methods and systems for forming ROM cell-based devices. The present invention additionally relates to methods and systems for configuring ROM cell architectures. This invention additionally pertains to a type of mask ROM. More specifically, the present invention is related to a contact or via type of mask ROM, which permits shortening of the cycle time of the manufacturing process.
BACKGROUND OF THE INVENTION
Read only memory (ROM) is so named because its cells can read data only from the memory cells. ROM is essentially a semiconductor circuit into which code or data can be permanently installed by a particular manufacturing process. ROM circuits are typically utilized to permanently store code in electronic equipment, such as computers, microprocessor systems, and so forth. The code or information stored in the ROM circuit is non-volatile when the power supply is powered off. There are various types of ROM devices, including Mask ROM, PROM (Programmable ROM), EPROM (Erasable Programmable ROM) and EEPROM (Electrically Erasable Programmable ROM). Such devices differ from one another in the type of methods utilized by the particular ROM to store data. Mask ROM is the most fundamental type of ROM.
For mask ROM, the memory data are loaded in the memory cells during manufacture. The data-writing step is called programming or coding. Usually, the interval from the time when the coding data in the mask ROM are obtained from the user to the time of shipment of the product is referred to as the cycle time, or turn-around-time. For ROM products, shortening the turn-around-time is an important task from the viewpoint of the commercial value of the products and productivity.
Depending on the data coding method, the mask ROMs can be classified into the diffusion type, contact type and via contact type. For each of these methods, there is a trade-off relationship between the cycle time and the degree of integration. When the actual ROM products are manufactured, it is necessary to select the appropriate method corresponding to the characteristics and demands on the specific type of products.
Memory cells are typically fabricated on a portion of a ROM device that includes an array of single transitory, typically a field effect transistor (FET), arranged in rows and columns. The arrays of FETs are built by first forming an array of closely spaced parallel electrically conducting line regions in the semiconductor substrate called “bit lines”. The bit lines serve as the source/drain regions of the FETs, and also serve as the electrical interconnections to the peripheral circuits for outputting the stored binary data. The buried bit lines are usually formed in the semiconductor substrate by ion implantation and a thermal oxide is then grown on the semiconductor substrate forming the gate oxide of the FET between the bit lines. The thermal oxide also provides the electrical insulation layer over the bit lines.
A plurality of closely spaced parallel conducting lines referred to as “word lines”, usually formed from a doped polysilicon layer, can then be formed on the semiconductor substrate having an orthogonal direction to the buried bit lines. The word lines serve as the gate electrode of the FETs and also function as the electrical interconnection to the peripheral address decode circuit. The array of ROM cells are then coded with information, such as micro-instruction, by permanently rendering selected transistors non-conducting during processing, while non-coded cells can be switch on when accessed by way of the address decode circuits. The coded information represented by a change or no change in the voltage level at the output circuit is used to represent the binary 1's and 0's. The code for the ROM is introduced during device processing by using a ROM code mask during one of the processing steps.
There are only two states in a conventional mask ROM device, the “ON” state and the “OFF” state. The “OFF” state is typically defined by code implantation to increase the cell threshold voltage (V
th
) is above 5 Volt, while the “ON” state is defined the cell Vth to be below 1 Volt. In a high-density mask ROM (32 M or 64 M), a conventional two state mask ROM will consume a large wafer area due to the large chip size. If one memory cell can store more than three kinds of data, called a multiple states mask ROM, it is possible to greatly increase the storage capacity of a mask ROM. For example, if one memory cell can store four kinds of data, it is possible to double the storage capacity in one chip without increasing the chip area. The mask ROM is coded with its data, i.e., has its data stored in it, by using a specialized mask (representing particular required for a user) during the fabrication process.
Data stored in a mask ROM cannot be changed, rather it is only possible to read the data. A type of mask ROM causes a predetermined transistor to have a status that differs from other transistors by implanting impurity ions, so that a datum is coded—that is, the mask ROM causes a predetermined transistor to have an OFF state by implanting impurity ions during fabrication. Transistors for which impurity ions are not implanted during fabrication have an ON state, and vice versa; therefore, the data are coded.
A number of ROM programming techniques are known in the art. Diffusion layer programming, ion implantation, and contact programming are types of ROM manufacturing processes. Among these processes, contact programming is a technique in which a programming process is provided near the final operational steps of semiconductor device manufacturing. The contact programming system is generally a method, which can realize a short turn-around-time.
FIG. 1
illustrates a prior art Mask ROM cell configuration
20
. In the example depicted in
FIG. 1
, a single ROM cell
22
is illustrated, which is formed from a polysilicon metal layer
26
. A polysilicon metal layer
26
and single ROM cell
22
are situated below a diffusion region
32
. A polysilicon metal layer
30
is situated below a diffusion region
34
and an active region
36
. The example illustrated in
FIG. 1
includes a total of four polysilicon metal layers
24
,
26
,
28
, and
30
. Those skilled in the art will recognize the configuration depicted in
FIG. 1
as an implementation of Contact/Via programming, a well-known method for programming a ROM cell, such as the single ROM cell
22
. An advantage of the Contact/Via programming technique is that it results in a short turn-around-time. A major disadvantage of this ROM programming method, however, is that it requires a large cell size.
FIG. 2
depicts a prior art diffusion-programming configuration
40
. In the example depicted in
FIG. 2
, a series of polysilicon layers
44
,
46
and
48
are situated adjacent a diffusion region
46
and
58
. Two single ROM cells
52
and
54
are respectively situated above polysilicon layers
48
and
46
. Those skilled in the art will recognize the configuration illustrated in
FIG. 2
as depicting an implementation of diffusion programming for ROM cells. An advantage or diffusion programming is that smaller cell sizes can be utilized. However, a major disadvantage of diffusion programming is that it requires a very long turn-around-time.
FIG. 3
illustrates a prior art ion implant programming configuration
70
. Those skilled in the art will recognize configuration
70
as comprising an implementation of implant programming for ROM cells. In the configuration illustrated in
FIG. 3
, four polysilicon layers
72
,
74
,
76
, and
78
are shown. Implant programming offers several advantages, namely, smaller cell size and an acceptable turn-around-time. Implant programming, however, requires an extra mask, which can ultimately result in extra costs in the manufacturing process.
The present inventors have thus concluded, based on the foregoing ROM programming techniques that several key factors are desired to improve the ef

Affiliated with

Also associated with

Rating

Metal interconnection read only memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Metal interconnection read only memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metal interconnection read only memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3078877