Metal interconnect structure

Details Metal interconnect structure Metal interconnect structure

2002-09-23

2003-09-16

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S762000, C257S761000, C257S758000

Reexamination Certificate

active

06621167

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to damascene Cu-based interconnects in integrated circuits. More particularly, the present invention relates to a Cu-based interconnect structure capable of reducing dishing effects that might occur within a surface of a via region of a copper wiring having a large line width.
2. Description of the Prior Art
In the manufacturing of integrated circuits, interconnects within a level are made by damascene features called trenches that are filled with an electrically conductive material like metal. Interconnects between levels are made by damascene features called vias. These interconnects are made by first etching a line, in the case of trenches, or a hole, in the case of vias in a substrate. An electrical conductor is then deposited over the entire substrate. The excess conductor is removed by planarizing the substrate with, for example, a chemical-mechanical polishing (CMP) process.
Ideally, the CMP process produces interconnect lines with a top surface that is co-planar with top surface of the substrate. Unfortunately, widely spaced interconnect lines such as power bus lines that are designed to carry high current densities tend to display reduced copper fill after electroplating and subsequent CMP planarization. Furthermore, in the case of an interconnect region having a dense line layout, post-CMP metal residues, which are also known as “bridging”, are frequently observed between two adjacent interconnect lines, which can lead to undesirable leakage current. One approach to solving the above-mentioned problems is to add a number of dielectric features into the wide interconnect lines. The dielectric features are also referred to as “oxide slots” by those skilled in the art.
Please refer to FIG.
1
and
FIG. 2
, where
FIG. 1
is a schematic diagram partially illustrating an enlarged top view of a Cu-based interconnect structure according to the prior art and
FIG. 2
is a schematic, cross-sectional view along line A-A″ of FIG.
1
. As shown in FIG.
1
and
FIG. 2
, an integrated circuit comprises a lower-layer metal wiring
10
intersecting an upper-layer metal wiring
12
. Between the lower-layer metal wiring
10
and the upper-layer metal wiring
12
, a layer of dielectric
30
is provided. Typically, assuming that the lower-layer metal wiring
10
and the upper-layer metal wiring
12
are power bus lines, both the lower-layer metal wiring
10
and the upper-layer metal wiring
12
have a line width of about 5 microns (&mgr;m). In this case, a 5 &mgr;m×5 &mgr;m overlapping region
50
(hereinafter referred to as a via region) is defined by the two layers of interconnect lines
10
and
12
for accommodating via plugs
20
. As mentioned, to reduce CMP dishing effects, a plurality of oxide slots
10
a
and
12
a
are distributed in the lower-layer metal wiring
10
and the upper-layer metal wiring
12
respectively outside the via region
50
.
According to the prior art, the via plugs
20
within the via region
50
usually reach a maximum number based on a predetermined design rule in order not to “open” the two layers of interconnect lines
10
and
12
. Hence, oxide slots are forbidden from being introduced into the via region
50
during the layout of the interconnect patterns. A maximum number of via plugs
20
in this via region
50
assures steady operations during the pass of a high density current between the two layers of interconnect lines
10
and
12
. However, the prior art interconnect structure, in which introduction of oxide slots is not allowed results in a dishing phenomenon. This dishing phenomenon results in a concave shaped surface of the interconnect, as indicated by the numeral
40
.
Please refer to FIG.
3
.
FIG. 3
is a schematic diagram partially illustrating an enlarged top view of a Cu-based dense line structure according to the prior art. As shown in
FIG. 3
, two upper-layer copper lines
120
and
122
and two lower-layer copper lines
100
and
102
are provided. The upper-layer copper line
120
and the lower-layer copper line
100
define a via region
51
. The upper-layer copper line
120
and the lower-layer copper line
102
define a via region
52
. The upper-layer copper line
122
and the lower-layer copper line
100
define a via region
53
. The upper-layer copper line
122
and the lower-layer copper line
102
define a via region
54
. The upper-layer copper line
120
is spaced apart from the upper-layer copper line
122
with a distance of about 0.26 microns, for example. Since there is no oxide slot formed within the via regions
51
,
52
,
53
, and
54
, post-CMP metal residues are left in the regions
71
and
72
between the two adjacent copper lines
120
and
122
.
Consequently, there is a strong need to provide an improved interconnect structure that is capable of reducing dishing effects and bridging when manufacturing integrated circuits.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide an improved metal interconnect structure to solve the above-mentioned problems.
According to the claimed invention, a metal interconnect structure is provided. The metal interconnect structure generally includes a lower-layer copper wiring, an upper-layer copper wiring partially overlapping with the lower-layer copper wiring to define a via region thereof, a dielectric layer disposed between the lower-layer copper wiring and the upper-layer copper wiring, a plurality of via plugs arranged in the dielectric layer within a first area of the via region for electrically connecting the lower-layer copper wiring and the upper-layer copper wiring, and a plurality of first dielectric structures embedded in the upper-layer copper wiring within a second area of the via region, in which the first area does not overlap with the second area.
According one preferred embodiment of this invention, the metal interconnect structure further comprises a plurality of second dielectric structures embedded in the lower-layer metal wiring within the second area of the via region.


REFERENCES:
patent: 6037668 (2000-03-01), Cave et al.
patent: 6468894 (2002-10-01), Yang et al.
patent: 6486558 (2002-11-01), Sugiyama et al.
patent: 6495918 (2002-12-01), Brintzinger
patent: 2001/0036737 (2001-11-01), Iguchi et al.
patent: 2002/0011672 (2002-01-01), Oku et al.

Affiliated with

Also associated with

Rating

Metal interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Metal interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metal interconnect structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3013362