Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-07-09
2003-09-30
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S185110, C365S185130
Reexamination Certificate
active
06628563
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit memory devices. More particularly this invention relates to circuits and devices for simultaneous storing and/or retrieving of digital data to and from integrated circuit memory. Even more particularly, this invention relates to simultaneous reading and programming of non-volatile integrated circuit memory or flash memory.
2. Description of Related Art
Non-volatile memories, especially Flash memories, have been widely used in various electronic applications such as computers, hand-held computing and control devices, communication devices, and consumer products. Due to its characteristic of non-volatility and on-system re-programmability, the flash memories are suitable to store both the program code and data code for a system. However, flash memory has its own disadvantage. Compared with volatile memories such as dynamic random access-memories and static random access memories, flash memories require a relative long period of time in processing a program/erase or ‘write’ operation. It typically takes several microseconds to seconds to write the data. During this time period, the whole memory is occupied and no other memory operations such as a read may be performed. Therefore, a ‘simultaneous read and write operation’ is highly demanded for flash memory.
An example of a simultaneous read and write operation for a flash memory is shown in U.S. Pat. No. 6,088,264 (Hazen et al.). The memory array contains more than two individual arrays and each array can independently perform read or write operations. Therefore, the data stored in one array can be read while the other array is doing the write operation. Each array of Hazen et al. requires additional decoder circuits, data buses, and control circuits to perform the simultaneous read and write operation. The extra area consumed, thus, limits the number of the arrays being used. Because the number of arrays is limited, each array is generally denser. This diminishes the amount of data that can be simultaneously read and/or written. When one array is being programmed or written to, the whole is array is unavailable being read.
U.S. Pat. No. 5,847,998 (Van Buskirk), disclosed another approach to enable arrays having a much smaller size for simultaneous read and write operation. It directly divided the array into several small-size blocks, such as 512 kb per block, and enables each block to be simultaneously read or programmed. Unfortunately, this approach can be only used for a flash memory having a ‘NOR’ structured array only. It cannot be used for any other flash memory array structures such as flash memories having an ‘AND’ array structure, because the cell operation and the bias conditions for the NOR array and the AND array are different.
It is well known in the art that flash memories have different array structures, and each array structure has its own features and characteristics. These array structures can be basically fallen into two categories, the ‘NOR-type’ array, as illustrated in U.S. Pat. No. 6,301,153 (Takeuchi et al.) and the ‘NAND-type’ array, as illustrated in U.S. Pat. No. 6,288,944 (Kawamura). For the NOR-type array, the memory cells are connected to bit lines in parallel. The NAND-type array, on the other hand, connects the memory cells serially. Due to this major difference, the NOR-type array tends to provide faster read speed and thus the NOR-type array dominates the high-speed application market. The NAND-type array tends to have smaller cell size. Due to its serial structure, the NAND-type, thus, dominates the low-cost, slow-speed, higher-density market.
The conventional NOR-type array includes several different structures as illustrated in Takeuchi et al. Takeuchi et al. illustrates the NOR, AND, and DINOR array structures. Other known structures include the Dual-String NOR and the OR. Each structure is an optimum solution for its own technology, and its own read, erase and program conditions and algorithm. The structures are further categorized according to the programming mechanism used. Only the NOR array and some Dual-String NOR arrays use Channel-Hot-Electron (CHE) injection in programming. All others use Fowler-Nordheim (FN) tunneling in programming. For this invention the NOR-type flash memory arrays that use Channel-Hot-Electron programming are termed ‘NOR-like’ arrays. The NOR-type arrays that use Fowler-Nordheim tunneling for programming are termed ‘AND-like’ array.
The conventional NOR-like array and the AND-like array structures of the prior art are not suitable for the simultaneous read and write (program/erase) operation. The simultaneous read and write operation is not possible because the array structures NOR-like array and the AND-like array cannot allow multiple blocks from being accessed, one for read and one for programming, at the same time. For example,
FIG. 1
illustrates a conventional NOR array as an example of the NOR-like arrays.
The NOR structured flash memory is divided into multiple blocks
10
and
20
. Each block
10
and
20
consists of memory cells M
11
, . . . , MN
4
, and M
21
, . . . , MM
4
. The control gates of each row of the memory cells M
11
, . . . , MN
4
, and M
21
, . . . , MM
4
are connected together and to the word lines
41
,
42
,
43
, and
44
. The word lines
41
,
42
,
43
, and
44
are connected to word line amplifier
40
to receive the word line control signals to cause selected rows of the memory cells M
11
, . . . , MN
4
, and M
21
, . . . , MM
4
to be either read or written (programmed/erased).
Each column of the memory cells M
1
, . . . , MN
4
, and M
21
, . . . , MM
4
of each array block
10
and
20
are interconnected by sub-bit lines or local bit lines
11
,
12
,
13
, and
14
for array block
10
and local bit lines
21
,
22
,
23
, and
24
for array block
20
. The local bit lines
11
,
12
,
13
, and
14
for array block
10
are connected respectively to the sources of the switch transistors Q
1
, Q
2
, Q
3
, and Q
4
. The drains of the switch transistors Q
1
, Q
2
, Q
3
, and Q
4
are connected respectively to the global bit lines
61
,
62
,
63
, and
64
. The local bit lines
21
,
22
,
23
, and
24
for array block
20
are connected respectively to the sources of the switch transistors Q
5
, Q
6
, Q
7
, and Q
8
. The drains of the switch transistors Q
5
, Q
6
, Q
7
, and Q
8
are connected respectively to the global bit lines
61
,
62
,
63
, and
64
.
The global bit lines
61
,
62
,
63
, and
64
are connected to the bit line amplifier
60
to receive the bit line control signals to cause the memory cells M
11
, . . . , MN
4
, and M
21
, . . . , MM
4
to be either read or written (programmed/erased).
The encoded address signals
30
are received and decoded by the address decoder
30
. The decoded address signals
34
are transferred to the word line amplifier
30
and the bit line amplifier
60
. The decoded address signals provide the word line and bit line control signals to activate the desired memory cells M
11
, . . . , MN
4
, and M
21
, . . . , MM
4
to be either read or written (programmed/erased). The read/write signal
56
and other timing and control signals (not shown) are received by the read/write control circuit
50
to provide the necessary timing and control signals
53
and
54
to the bit line amplifier
60
and the word line amplifier
40
.
The gate select lines
51
and
52
are provided by the read/write control circuit
50
to activate the desired switch transistors Q
1
, Q
2
, Q
3
, and Q
4
or the desired switch transistors Q
5
, Q
6
, Q
7
, and Q
8
. The selected switch transistors Q
1
, Q
2
, Q
3
, and Q
4
or switch transistors Q
5
, Q
6
, Q
7
, and Q
8
connect the local bit lines
11
,
12
,
13
, and
14
for the array block
10
or the local bit lines
21
,
22
,
23
, and
24
for array block
20
to the global bit lines
61
,
62
,
63
, and
64
.
The sources of each memory cell of each row of the memory cells M
11
, . . . , MN
4
, and M
21
, . . . , MM
4
are connected together and to
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Ackerman Stephen B.
Aplus Flash Technology Inc.
Hoang Huan
Knowles Billy
Saile George O.
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