Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1995-05-15
1997-10-07
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257392, 257396, 257403, 257404, H01L 2976, H01L 2994, H01L 31062
Patent
active
056751729
ABSTRACT:
A MIS device comprising a pair of first doped layers of a second conductivity type forming source/drain regions in a semiconductor base structure of a first conductivity type, and a gate electrode formed in a region between the first doped layers of the second conductivity type on a gate insulating film formed on the semiconductor base structure having a three-layer structure consisting of a second doped layer of the first conductivity type, a third doped layer of the second conductivity type and a fourth doped layer of the first conductivity type having an impurity concentration higher than that of the semiconductor base structure, which are formed in that order in the direction of depth from the surface of a channel region extending between the source/drain regions, the thickness of the third doped layer is determined so that the third doped layer is depleted by the respective built-in potentials of pn junctions formed by the second doped layer and the third doped layer and by the fourth doped layer and the third doped layer, respectively. Even when the MIS device of this structure is miniaturized, the subthreshold swing can be reduced to a value small enough to enable the lowering of the threshold voltage, the electric field intensity in the interface of the gate insulating film is reduced to enhance the carrier mobility and hence the MIS device is suitable for low-voltage operation.
REFERENCES:
patent: 4276095 (1981-06-01), Beilstein, Jr. et al.
patent: 5489795 (1996-02-01), Yoshimura et al.
English language abstract of Japanese publication No. 60-50960 (A), published Mar. 22, 1985.
"Substrate Engineering" for V.sub.TH -Scaling at Low Supply Voltage (1.3-3V) in USLIs, by R. Izawa et al., Extended Abstracts of 21st Conf. on Solid State Devices and Materials, Tokyo, 1989, pp. 121-124.
"Design and Performance of 0.1.mu.m CMOS Devices . . . " by M. Aoki, et al., IEEE Electron Device Letters, vol. 13, No. 1, Jan. 1992, pp. 50-52.
Ishii Tatsuya
Miyamoto Masafumi
Hitachi , Ltd.
Ngo Ngan V.
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