Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2003-02-27
2004-03-30
Ngõ, Ngãn V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S532000
Reexamination Certificate
active
06713840
ABSTRACT:
BACKGROUND OF THE INVENTION
The present disclosure relates generally to the fabrication of a metal-insulator-metal (MIM) device structure and more particularly, inserting an MIM structure in a low-k material.
The increasing popularity of electronic equipment, such as computers for example, is increasing the demand for large semiconductor electronic circuits. One example is a large semiconductor memory.
FIG. 1
shows a simplified diagram of the organization of a typical large semiconductor memory
14
. The storage cells of the memory
14
are arranged in an array including horizontal rows and vertical columns. The horizontal lines connected to all of the cells in the row are referred to as word lines
11
, and the vertical lines connected to all of the cells in the column are referred to as bit lines
13
. Data flows into and out of the cells via the bit lines
13
.
Row address
10
and column address
12
are used to identify a location in the memory
14
. A row address buffer
15
and a column address buffer
17
, respectively, receive row address
10
signals and column address
12
signals. The buffers
15
and
17
then drive these signals to a row decoder
16
and column decoder
18
, respectively. The row decoder
16
and the column decoder
18
then select the appropriate word line and bit line corresponding to the received address signal. The word and bit lines select a particular memory cell of the memory
14
corresponding to the received address signals. As is known in the art of semiconductor memory fabrication, the row decoder
16
and the column decoder
18
reduce the number of address lines needed for accessing a large number of storage cells in the memory
14
.
The array configuration of semiconductor memory
14
lends itself well to the regular structure preferred in “very large scale integration” (VLSI) ICs. For example, the memory
14
can be a dynamic random access memory (DRAM). DRAMs have become one of the most widely used types of semiconductor memory due to their low cost per bit, high device density and flexibility of use concerning reading and writing operations.
Capacitors are critical components in the ICs such as the DRAM of today. These passive components are often to be integrated with active bipolar or MOS transistors for analog and digital circuits. Examples of capacitors used in the art are: polysilicon-insulator-polysilicon (PIP), polysilicon-insulator-polycide, polysilicon-insulator-metal MIS), and metal-insulator-metal (MIM) capacitors. Early DRAMs used storage cells each consisting of three transistors and were manufactured using P type channel metal-oxide-semiconductor (PMOS) technology. Later, a DRAM storage cell structure consisting of one transistor and one capacitor was developed. For mixed signal devices of 0.13 nanometers and below, copper damascene processes are usually used for high performance.
In devices that uses a low-k material, especially in the conventional method for manufacturing an MIM structure, the MIM structure is processed on the top of metal layers or far from low-k films. It is technically difficult to insert an MIM structure into a low-k material.
What is needed is a method and system for-manufacturing electric devices such as a capacitor embedded within a low-k material.
SUMMARY
A metal-insulator-metal capacitor (MIM) structure inserted in a low-k material and the method for forming same is disclosed. The low-k material has a first low-k material layer at the bottom of the MIM structure and a second low-k material layer on top of the MIM structure. The MIM structure further comprises a first sealing layer on top of the first low-k material layer, an out gas sealing layer on top of the first sealing layer; and a device such as a capacitor formed on top of the out gas sealing layer, the capacitor having a dielectric layer, a top plate, and a bottom plate, wherein the dielectric layer has a center portion having the same width as the top plate, and two extended portions, each with a predetermined width and a predetermined minimum thickness.
In one example, the etch stop layer on top of the capacitor reaches down to the out gas sealing layer so as to enclose the capacitor within these two layer of materials. In another example, the etch stop layer only reaches where the dielectric layer is.
Therefore, in accordance with the previous summary, objects, features and advantages of the present disclosure will become apparent to one skilled in the art from the subsequent description and the appended claims taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
illustrates a simplified diagram of the organization of a typical large semiconductor memory;
FIGS. 2-6
illustrate the process steps of one example of the present disclosure; and
FIGS. 7-11
illustrate the process steps of another example of the present disclosure.
REFERENCES:
patent: 6573587 (2003-06-01), Igarashi
patent: 2002/0074601 (2002-06-01), Fox et al.
patent: 2003/0146492 (2003-08-01), Malinowski et al.
Lee Charles C. C.
Wu Chi-Hsi
Haynes and Boone LLP
Ngõ Ngãn V.
Taiwan Semiconductor Manufacturing Company , Ltd.
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