Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-23
2001-07-10
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S529000, C257S532000, C438S393000, C438S618000, C438S687000, C438S694000
Reexamination Certificate
active
06259128
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a metal-insulator-metal capacitor for a metal damascene process and a method of manufacturing the same.
2. Description of the Related Art
Precision capacitors for complementary metal oxide semiconductor (CMOS) analog applications are generally metal-insulator-metal (MIM) capacitors or polysilicon-insulator-polysilicon (P-P) capacitors.
However, P-P capacitors are becoming less popular because they present a number of problems when used with complementary metal oxide semiconductor (CMOS) technologies. More specifically, P-P capacitors are generally performed before the CMOS structures and the heat and oxidation cycles which occur during the CMOS production process degrade the P-P capacitors. Further, the sophistication of analog circuits is improving which requires that the variation in the capacitance be decreased and preferably maintained at a voltage of approximately 25 ppM. However, P-P capacitors suffer from carrier depletion which changes the capacitance as surface voltage across the P-P capacitor changes. Therefore, P-P capacitors do not maintain the linearity required in today's sophisticated analog circuits. Further, P-P capacitors often trap charges within the insulator during their use.
Therefore, MIM capacitors, which are usually formed after the CMOS production process, are generally becoming more popular for analog circuits. However, MIM capacitors also present manufacturing problems. More specifically, conventional MIM capacitors with an SiO
2
insulator cannot be used over copper damascene metal wiring because copper diffuses through the capacitor structure and creates leakage. In other words, the copper is not a good electrode in the conventional capacitor structures. Therefore, conventional MIM capacitors are generally only used with aluminum wiring. This is a substantial disadvantage because copper damascene wiring is becoming more popular in CMOS technologies because copper is less expensive and has better conductivity and electromigration resistance when compared to aluminum wiring.
Therefore, there is a need for a process and structure which allows MIM capacitors to be used with copper damascene wiring.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for producing a metal-insulator-metal capacitor, which uses a damascene metal such as copper.
The capacitor structure may be formed on a semiconductor substrate. The capacitor structure according to the present invention may include a first interconnect wiring such as a copper damascene metal which is embedded within a first planar insulator structure. The capacitor structure may also include a first conductive barrier layer such as tantalum nitride (TaN) on the first planar insulator structure. The first conductive barrier layer may contact the exposed portion of the first interconnect wiring. The capacitor structure may include a first capacitor plate (such as aluminum) formed on the first conductive barrier layer. A capacitor dielectric structure may be provided on the first capacitor plate. A second capacitor plate (such as aluminum) may be formed on the dielectric structure and a second conductive barrier layer may be formed on the second capacitor plate. The capacitor structure may also include a second planar insulating structure formed over the second capacitor plate and a second interconnect wiring embedded within the second planar insulator structure.
A method of forming the metal-insulator-metal capacitor structure according to the present invention may include forming a metal damascene region on a semiconductor substrate, forming a first barrier layer on the metal damascene region such that the first barrier layer contacts the metal damascene region, forming a metal-insulator-metal capacitor on the first barrier layer, and applying an insulating layer on the metal-insulator-metal capacitor.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.
REFERENCES:
patent: 5523253 (1996-06-01), Gilmour et al.
patent: 5723898 (1998-03-01), Gilmore et al.
patent: 5795819 (1998-08-01), Motsiff et al.
patent: 6037258 (2000-03-01), Liu et al.
Adler Eric
Trombley Henry W.
International Business Machines - Corporation
McGinn & Gibb PLLC
Walter, Jr. Esq. Howard J.
Wojciechowicz Edward
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