Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-15
2004-08-10
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S758000
Reexamination Certificate
active
06774425
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an integrated component with a multiplicity of interconnects and a capacitor with the capacitor having a first electrode, a dielectric interlayer and a second electrode.
The invention also relates to a method for fabricating an integrated component of this type.
The article by Aryon Kar-Roy et al., “High Density Metal Insulator Metal Capacitor Using PECVD Nitride for Mixed Signal and RF Circuits”,
International Interconnect Technologies Conference
, 1999, pp. 245 to 247, has disclosed a semiconductor structure in which the metal-insulator-metal capacitor is formed by a first metal layer, a dielectric interlayer and an intermediate metal layer. The intermediate metal layer is connected to a second metal layer through vias. The first and second metal layer also form the interconnects by which the passive components in the layer structure are connected to one another. Accordingly, the first metal layer and the second metal layer run at substantially the same level over the entire cross section of the semiconductor structure. However, the extent of the intermediate metal layer, which forms one of the electrodes of the capacitor, is locally limited and this layer is arranged at a level between the first and second metal layers.
To fabricate the known layer structure, a layer of either Ti or TiN is first applied to the first metal layer, which comprises aluminum and which forms the first electrode of the capacitor. Then, the dielectric interlayer, which, for example comprises either SiO
2
or SiN, is deposited on the layer of Ti or TiN. Then a layer of either Ti or TiN, the intermediate metal layer of aluminum and a further layer of either Ti or TiN, which serves as an antireflection layer, are applied in that order. These layers are applied to the entire surface. To pattern the second metal layer which forms the second electrode, a photoresist is applied to the antireflection layer and exposed. Then, etching is carried out, stopping in the dielectric interlayer. This is followed by patterning of the first metal layer below the dielectric layer, which metal layer forms the first electrode. For this purpose, once again a photoresist is applied, exposed and then the first metal layer is etched. This results in the formation of a layer structure with a capacitor, the first electrode of which is formed by the first metal layer and the second electrode of which is formed by the intermediate metal layer.
A drawback of the known layer structure and of the method for its fabrication is that it is difficult to produce vias between the intermediate metal layer and the second metal layer, since in this process step it is expedient for the vias between the interconnects in the first metal layer and the interconnects of the second metal layer also to be produced. However, the vias between the intermediate metal layer and the second metal layer are less deep than the vias between interconnects in the first metal layer and interconnects of the second metal layer. Consequently, the intermediate metal layer has to be effectively protected by means of an etching stop. However, this cannot always be achieved. Accordingly, the intermediate metal layer and therefore the capacitor arc often destroyed.
SUMMARY OF THE INVENTION
Working on the basis of the prior art, the invention is based on the object of providing an integrated component having a metal-insulator-metal capacitor which is easy to fabricate and of providing a method for its fabrication.
This object is achieved by an integrated component having a multiplicity of interconnects and a capacitor which has a first electrode, a dielectric interlayer and a second electrode, with an improvement of the electrodes of the capacitor including a layer sequence which is identical to the layer sequence of the closest interconnect.
The object is also achieved by a method for fabricating an integrated component, which has a capacitor with a metal-insulator-metal layer sequence and interconnects. The method comprises the steps of depositing a first layer sequence for a first electrode of the capacitor, depositing a dielectric interlayer on the first layer sequence; etching to pattern the first layer sequence and the dielectric interlayer to form the first electrode and the insulator with the etching stopping in the first layer sequence; depositing a second layer sequence for a second electrode of the capacitor; and etching the second layer sequence to pattern the second layer sequence to form the second electrode and the interconnects.
Since the electrodes of the capacitor together have substantially the same layer sequence as the layer sequence of the closest interconnect, the layer sequence in the region of the capacitor differs only through the dielectric interlayer from the layer sequence in the region of the interconnects. Consequently, the vias between the second electrode and a metal layer above it and the vias between the adjacent interconnect and the metal layer above it are of substantially the same length. Moreover, the thickness of the electrodes approximately corresponds to the thickness of an interconnect. However, interconnects usually have a very high thickness compared to other layers. Since, in the subject matter of the invention, the electrodes are of approximately the same thickness as an interconnect, it is not disadvantageous if the second electrode is partially etched when the vias are being etched out. This is because their great thickness means that the remaining second electrode still has a thickness which is sufficient for it to function. For these reasons, the second electrode also does not have to be protected by an effective etching stop when the passages of the vias are being etched.
The fabrication method for fabricating the capacitor is expediently managed in such a way that first of all the lower, first electrode and the dielectric interlayer are deposited and patterned. The layers required in order to form the second electrode can be applied to the lower, first electrode formed in this way. Finally, after these layers have been patterned, the result is a capacitor whose electrodes together have the same layer sequence as an interconnect which has been formed together with the capacitor. As has already been mentioned, this significantly facilitates the production of the vias between the second electrode and a metal layer above it and between adjacent interconnects and the metal layer above them.
Expedient configurations of the invention form the subject matter of the dependent claims.
The text which follows explains an exemplary embodiment of the invention in detail with reference to the appended drawing.
REFERENCES:
patent: 6136640 (2000-10-01), Marty et al.
patent: 6175131 (2001-01-01), Adan
patent: 6569746 (2003-05-01), Lee et al.
patent: 0 800 217 (1997-10-01), None
patent: 0 892 442 (1999-01-01), None
Arjun Kar-Roy et al, “High Density Metal Insulator Metal Capacitors Using PECVD Nitride for Mixed Signal and RF Circuits”,International Interconnect Technologies Conference, San Francisco, CA, May 24, 1999, pp. 245-247.
Lachner Rudolf
Schrenk Michael
Schwerd Markus
Ho Tu-Tu
Infineon - Technologies AG
Nelms David
Schiff & Hardin LLP
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