Metal-gate non-volatile memory cell

Details Metal-gate non-volatile memory cell Metal-gate non-volatile memory cell

1998-04-17

2001-04-03

Chaudhuri, Olik (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S324000, C257S649000, C257S765000, C257S771000

Reexamination Certificate

active

06211548

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to non-volatile semiconductor memory technology and more particularly to a structure of and a method for producing a non-volatile memory cell having a metal layer used as the control gate.
DESCRIPTION OF THE RELATED ART
Conventional non-volatile semiconductor memory cell technologies, which use polysilicon floating gate as the storage element, typically comprise two or three layers of polysilicon.
FIG. 1
shows the cross section of a conventional double-poly ETOX non-volatile memory cell. The first polysilicon layer
10
, commonly referred to as the floating gate, is used as the storage element. As shown in
FIG. 1
, the floating gate
10
is encompassed on top by an ONO (Oxide-Nitrate-Oxide) coupling dielectric layer
11
and on bottom by a tunnel oxide dielectric layer
12
, typically around 100 Å thick.
The second polysilicon layer
13
is used as the control gate of the memory cell. When a number of memory cells are placed next to one another along one row in a memory array, the second polysilicon layer
13
forms a continuous line, commonly referred to as a wordline. As shown in
FIG. 1
, n+ source region
14
and n+ drain region
15
are formed in a P-type substrate
18
through an Arsenic implant step.
Metal
1
layer
16
contacts the source region
14
and the drain region
15
, and is usually isolated from the control gate
13
by a thick BPSG insulating layer
17
. Importantly, source region
14
and drain region
15
are self-aligned to the edge of the double polysilicon stack. This feature enables scaling of the ETOX cell with minimal complexity. This self-aligned feature is achieved by carrying out the source/drain implant after the formation of the stack of control gate
13
and floating gate
10
.
With the advent of sub-micron technology and the rapidly increasing memory sizes, and the development of systems-on-chip, a number of limitations have arisen, to which no viable solutions have yet been offered.
One of these limitations is the long wordline RC time delays associated with large memory arrays. As mentioned earlier, in non-volatile memory arrays the second layer polysilicon forms the wordline. The high resistance and capacitance associated with second layer polysilicon results in what is known as the wordline RC time delay. With memory devices rapidly increasing in size, the memory arrays have become quite large. This, coupled with the continued scaling of semiconductor memory technology, has resulted in memory arrays with very long and thin polysilicon wordlines, which in turn have resulted in long RC time delays. The RC time delay, which is in the critical speed path of most memory devices, has become a limiting factor in achieving satisfactory memory device access times.
A number of approaches have been used to minimize the wordline RC time delay. One scheme breaks wordlines in half and drives the first half by a row decoder and the second half by a repeater. Each wordline requires one repeater and each repeater consists of two serially connected inverters. Given that two serially connected inverters need to be laid-out within the small pitch of a wordline, even the most efficient layout leads to repeaters excess die area. Therefore, repeaters, though effective in reducing the wordline RC delay, consume a large portion of the die area.
A second approach uses of tungsten silicide. Tungsten silicide reduces the resistance of the wordline RC by a factor of 10 as compared to polysilicon. However, with the rapid increase in memory sizes over the past decade, silicide is no longer an effective means of reducing the RC time delay.
A third and more effective approach in minimizing the wordline RC delay has been strapping the polysilicon wordline with a metal layer. Due to the very low resistance of metal, strapping the polysilicon effectively shorts the polysilicon wordline, thereby significantly reducing the resistance of the wordline RC. However, in order to strap the poly wordline with metal, contact holes need to be made between the metal and the polysilicon. Since the wordline pitch is usually the tightest pitch, such contact holes increase the wordline pitch and thereby result in significant loss of silicon area. In addition, the metal strap extending across the thin polysilicon wordline overlays a very rough topography caused by the double polysilicon stack. This has been the source of significant yield loss in mass producing non-volatile memories. Therefore, here again the speed improvements are at the cost of a larger die size and yield loss.
None of the above approaches offer an effective solution in minimizing the wordline RC time delay without any significant drawbacks.
A second impairing limitation involves some of the complexities arising in integrating different technologies. A general trend in the semiconductor industry has been integrating more functions into one chip, thereby replacing a number of discrete devices with one device. To enable such integration, combining different technologies such as SRAM, non-volatile and standard CMOS logic into one single process has become necessary. However, combining these technologies into a single process have proven difficult and complex. Standard CMOS logic technology and non-volatile memory technology have in fact been combined at the expense of a complex process.
One example of complexities arising in combining technologies is the classic case of combining SRAM technology using four transistor memory cells and non-volatile memory technology into a single process, a much favored trend in designing microcontrollers. The four transistor SRAM cell requires the use of a highly resistive polysilicon as the load element. In contrast, the non-volatile memory technology requires low resistive polysilicon to minimize such speed impediments as poly interconnect delay, gate resistance, the wordline resistance. Therefore, two conflicting characteristics are required of the polysilicon. Some memory manufacturers have adopted a singly poly non-volatile cell approach to overcome this limitation. However, the size of a single poly cell is typically three to four times larger than the conventional double poly cell. With no viable solution being offered, the development of cost effective products such as flash/SRAM IC devices has been hindered.
Theoretically, using metal as the control gate of the memory cell instead of polysilicon would overcome the above two mentioned limitations. The RC time delay limitation is overcome without any area penalty since the wordlines would be formed directly from metal, and as such no contact holes for strapping the wordlines would be needed. With respect to the limitation arising in integration of SRAM and nonvolatile memory technologies, a highly resistive second layer poly can be used exclusively as the load element for the four transistor SRAM cell, while metal and first layer poly can be used as the control gate and the floating gate of the memory cell respectively, thereby, eliminating the above mentioned conflicting characteristics required of the second layer poly.
In the early days of the IC industry, when 5 &mgr;m lithography metal-gate technology was in use, metal gate MOS transistors were common. However, the practice of using metal as the gate electrode or control gate of MOS devices has long been abandoned. The primary reason for abandonment of this technology was the lack of scalability. Unlike the conventional poly gate technology which lends itself well to scaling, the metal gate technology did not.
As mentioned earlier, the scalability of the poly gate technology stems from the self-aligned feature of its fabrication process. More specifically, the source/drain regions are self-aligned to the poly control gate because the source/drain ion implant step is carried out after the deposition and patterning of the poly gate whereby, the edges of the poly control gate are used to define the portions of the boundaries of the source/drain regions which delineate the transistor channel region. Th

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