Metal fuse for semiconductor devices

Details Metal fuse for semiconductor devices Metal fuse for semiconductor devices

2007-04-17

2007-04-17

Lee, Hsien-Ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S173000, C257S751000, C257S499000, C257SE21149, C438S642000, C438S687000

Reexamination Certificate

active

10856065

ABSTRACT:
A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2 exposing at least a portion of the exposed adjacent metal structures. A metal fuse portion is formed between at least two of the adjacent metal structures without additional photolithography, etch or deposition processes. The metal fuse portion including a portion having a nominal mass and a sub-portion of the portion having a mass less than the nominal mass so that the metal fuse portion is more easily disconnected at the less massive sub-portion during programming of the metal fuse portion.

REFERENCES:
patent: 4792835 (1988-12-01), Sacarisen et al.
patent: 5936296 (1999-08-01), Park et al.
patent: 5963825 (1999-10-01), Lee et al.
patent: 6037648 (2000-03-01), Arndt et al.
patent: 6100116 (2000-08-01), Lee et al.
patent: 6100118 (2000-08-01), Shih et al.
patent: 6261873 (2001-07-01), Bouldin et al.
patent: 2001/0042897 (2001-11-01), Yeh et al.
patent: 08-255837 (1995-03-01), None

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