Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-21
2003-01-07
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S762000
Reexamination Certificate
active
06504205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to an integrated circuit including capacitors. In particular, the present invention relates to capacitors with damascene structures.
2. Description of the Related Art
Capacitors are deployed in various integrated circuits. For example, capacitors can be used as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution. Capacitors also have wide applications in analog/logic, analog-to-digital, mixed signal, radio frequency circuits and so on.
A conventional method of manufacturing a semiconductor apparatus including a capacitor
20
formed of metal-insulator-metal layers is described with reference to FIGS.
1
A~
1
D. As shown in
FIG. 1A
, an aluminum layer is deposited on an insulator
12
which contains interconnections and is formed on a silicon substrate having devices (not shown) thereon and therein. The aluminum layer is then patterned by masking and etching to form wires
14
a
and
14
b.
As shown in
FIG. 1B
, an insulator
16
with a tungsten plug
18
(hereafter “W-plug”) used to connect the aluminum wire
14
a
and the to-be-formed capacitor is formed on the aluminum wires
14
a
and
14
b
and the insulator
12
. As shown in
FIG. 1C
, a first conductive plate
21
, a dielectric layer
22
and a second conductive plate
23
are sequentially deposited on the insulator
16
and the W-plug
18
, and then patterned by masking and etching to obtain a capacitor
20
. The first conductive plate
21
, the bottom electrode, is connected with the aluminum wire
14
a
through the W-plug
18
. Another insulator
26
is deposited on the insulator
16
and the capacitor
20
. The insulators
16
and
26
are patterned and W-plug
28
a
and W-plug
28
b
are formed therein. As shown in
FIG. 1D
, an aluminum layer (not shown) is deposited on the insulator
26
and the W-plugs
28
a
and
28
b.
The aluminum layer is then patterned by masking and etching to form wires
34
a
and
34
b.
The aluminum wire
34
a
is connected with the second conductive plate
23
through the W-plug
28
a.
The aluminum wire
34
b
is connected with the aluminum wire
14
b
through the W-plug
28
b.
This method for integrating the capacitor
20
into an integrated circuit requires several masking and etching steps to form the capacitor
20
, which may increase overall fabrication costs. Moreover, if a greater capacitance of the plane capacitor
20
is required, a greater area of the plane capacitor
20
is needed. This will sacrifice the spaces between the capacitor
20
and the nearby wires and make scaling down difficult. Furthermore, a drop height exists between the capacitor area and the non-capacitor area, resulting in an uneven topography of the insulator
26
.
A method of manufacturing a capacitor while simultaneously forming a dual damascene via is disclosed in U.S. Pat. No. 6,025,226. In the '226 patent, a conductor which is used to form a bottom electrode is deposited in the openings for the via and capacitor. However, the conductor should be sufficiently thick to fill the via opening and sufficiently thin to not planarize the capacitor opening. It is difficult to form such a conductor.
Besides, the aluminum used to fabricate the traditional interconnections cannot satisfy the trends of enhanced integration and speed of data transmission. Copper (Cu) has high electric conductivity to reduce RC delay and can be substituted for aluminum as conducting wires. The use of copper as the conducting wires requires the use of processes, that is, damascene processes, because copper cannot be patterned by etching processes. This is because the boiling point of copper chloride (CuCl
2
) produced by copper and the chlorine plasma usually used to etch metal is relatively high, about 1500° C. Therefore, Cu processes should be used to fabricate an integrated circuit including a capacitor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide metal capacitors with a damascene process.
It is another object of the invention to reduce the drop height existing between the capacitor area and the non-capacitor area.
Yet another object of the invention is to use the Cu processes to fabricate the integrated circuit including capacitors to reduce RC delay.
The present invention provides a metal capacitor with damascene structures. A first Cu wire and a second Cu wire are disposed in a first insulator. A second insulator with an opening is disposed on the first insulator, wherein the opening is positioned on the first Cu wire. A first metal layer is conformally disposed in the opening and contacts the surface of the first Cu wire. A dielectric layer is conformally disposed on the first metal layer in the opening. A second metal layer is conformally disposed on the dielectric layer in the opening. A third insulator is disposed on the second insulator and the second metal layer. A first Cu damascene structure and a second Cu damascene structure are disposed in the second and third insulators, wherein the first Cu damascene structure is composed of a third Cu wire and a first Cu plug and the second Cu damascene structure is composed of a fourth Cu wire and a second Cu plug, wherein the second metal layer is connected with the third Cu wire through the first Cu plug, and the fourth Cu wire is connected with the second Cu wire through the second Cu plug. A first sealing layer is disposed between the second Cu wire and the second insulator. A second sealing layer is disposed on the third and fourth Cu wires.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.
REFERENCES:
patent: 6008084 (1999-12-01), Sung
patent: 6008085 (1999-12-01), Sung et al.
patent: 6025226 (2000-02-01), Gambino et al.
patent: 6329234 (2001-12-01), Ma
Hsue Chen-Chiu
Lee Shyh-Dar
Silicon Integrated Systems Corp.
Tsai Jey
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