Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-28
2003-01-28
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S765000, C257S762000
Reexamination Certificate
active
06512260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to an integrated circuit including capacitors. In particular, the present invention relates to a metal capacitor in damascene structures.
2. Description of the Related Art
Capacitors are deployed in various integrated circuits. For example, decoupling capacitors provide improved voltage regulation and noise immunity for power distribution. Capacitors also have wide applications in analog/logic, analog-to-digital, mixed signal, radio frequency circuit operations, and others.
A conventional method of manufacturing a semiconductor apparatus including a capacitor
20
that is formed of metal-insulator-metal layers is described with reference to FIGS.
1
A~
1
D. As shown in
FIG. 1A
, an aluminum layer is deposited on an insulator
12
which contains interconnections and is formed on a silicon substrate having devices (not shown) thereon and therein. The aluminum layer is then patterned by masking and etching to form wires
14
a
and
14
b.
As shown in
FIG. 1B
, an insulator
16
with a tungsten plug
18
(hereafter “W-plug”) used to connect the aluminum wire
14
a
and the to-be-formed capacitor is formed on the aluminum wires
14
a
and
14
b
and the insulator
12
. As shown in
FIG. 1C
, a first conductive plate
21
, an insulator
22
and a second conductive plate
23
are sequentially deposited on the insulator
16
and the W-plug
18
, and then patterned by masking and etching to obtain a capacitor
20
. The first conductive plate
21
, the lower electrode, is connected with the aluminum wire
14
a
through the W-plug
18
. Another insulator
26
is deposited on the insulator
16
and the capacitor
20
. The insulators
16
and
26
are patterned and W-plug
28
a
and W-plug
28
b
are formed therein. As shown in
FIG. 1D
, an aluminum layer is deposited on the insulator
26
and the W-plugs
28
a
and
28
b
. The aluminum layer is then patterned by masking and etching to form wires
34
a
and
34
b
. The aluminum wire
34
a
is connected with the second conductive plate
23
through the W-plug
28
a
. The aluminum wire
34
b
is connected with the aluminum wire
14
b
through the W-plug
28
b.
The above-mentioned traditional processes for integrating the capacitor
20
into an integrated circuit require several masking and etching steps to form the capacitor
20
, which may increase overall fabrication costs.
As well, the aluminum used to fabricate the traditional interconnections cannot satisfy present-day requirements for enhanced integration and highly demanding speeds of data transmission. Copper (Cu) has high electric conductivity to reduce RC delay and can be substituted for the aluminum in the conductive wires. The use of copper in the conductive wires requires the use of processes, that is, damascene processes, because copper cannot be patterned by etching. This is because the boiling point of the copper chloride (CuCl
2
) produced by copper and the chlorine plasma usually used to etch metal is relatively high, about 1500° C.
A thin-film capacitor formed by combining with the Cu damascene process is disclosed in U.S. Pat. No. 6,180,976 B1. In the '976 B1 patent, the lower electrode of the thin-film capacitor is also formed by the damascene process. The '976 B1 patent has the advantage of saving a masking step. However, a chemical mechanical polishing process is required to remove undesired metal residue to form the lower electrode. Dishing is likely to occur on the lower electrode and result in an uneven surface. Therefore, the thickness of the insulator can not be kept uniform to stabilize the electrical properties of the capacitors.
SUMMARY OF THE INVENTION
The present invention provides a metal capacitor in damascene structures. A first Cu wire and a second Cu wire are located in a first insulator. A first sealing layer is located on the first and the second Cu wires. A second insulator is located on the first sealing layer. A third insulator is located on the second insulator, and acting as an etch stop layer. A first Cu plug and a second Cu plug are located in the first sealing layer, the second insulator and the third insulator. A capacitor is located on the third insulator and the first Cu plug, the capacitor having an upper electrode, a capacitor dielectric and a bottom electrode with the same pattern each other, wherein the bottom electrode is connected to the first Cu wire through the first Cu plug. A conducting wire is located on the third insulator and the second Cu plug, wherein the conducting wire is connected to the second Cu wire through the second Cu plug. A fourth insulator is located on the conducting wire. A fifth insulator with a flat surface is located on the upper electrode, the fourth insulator and the third insulator. A plurality of dual damascene structures including a third plug, a fourth Cu plug, a third Cu wire and a fourth Cu wire are located in the fifth insulator, wherein an upper electrode of the capacitor is connected to the third Cu wire through the third Cu plug, and the conducting wire is connected to the fourth Cu wire through the fourth Cu plug. A second sealing layer is located on the third and fourth Cu wires.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.
REFERENCES:
patent: 6180976 (2001-01-01), Roy
patent: 6433994 (2002-08-01), Tang et al.
Hsue Chen-Chiu
Lee Shyh-Dar
Tsai Jen-Hann
Silicon Integrated Systems Corp.
Tsai Jey
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