Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-08-29
2006-08-29
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S137000, C712S207000
Reexamination Certificate
active
07099995
ABSTRACT:
A data storage control unit is coupled to one or more host devices and to one or more physical storage units. Data is stored in one of the storage units and, for data integrity, copied to another storage unit. An updated state of the copy process (metadata) is maintained and updated in metadata tracks in a memory of the storage controller and periodically destaged to corresponding metadata tracks of a storage unit. If the copy process is interrupted, such as by a power failure, an error handling routine commences. Track state fields associated with each in-memory metadata track are initialized to an ‘invalid’ state and background staging of metadata tracks from the storage unit to the memory. After a track is staged, the associated track state field is changed to a ‘valid’ state. If a request is received to access a track of copy state data and the track has been staged (as indicated by the state of the associated track state field), the track is accessed. If the requested track has not been staged, requester waits while the requested track is staged; then the requested track is accessed. Once the error handling routine is completed, normal I/O operations with customer data may resume. Preferably, completion of the error handling routine is independent of the completion of the staging of copy state data tracks.
REFERENCES:
patent: 3611314 (1971-10-01), Pritchard et al.
patent: 4449182 (1984-05-01), Rubinson et al.
patent: 5623608 (1997-04-01), Ng
patent: 5745730 (1998-04-01), Nozue et al.
patent: 5867685 (1999-02-01), Fuld et al.
patent: 6047001 (2000-04-01), Kuo et al.
patent: 6061768 (2000-05-01), Kuo et al.
patent: 6516389 (2003-02-01), Uchihori
patent: 6557083 (2003-04-01), Sperber et al.
patent: 6584513 (2003-06-01), Kallat et al.
patent: 2002/0169927 (2002-11-01), Takai
patent: 2005/0138195 (2005-06-01), Bono
IBM Technical Disclosure Bulletin (1994) 37(10):681.
Budaya Angelique R.
Hsu Yu-Cheng
Mahar Aaron S.
Sharaby Gilad
Springer James A.
Moazzami Nasser
Shifrin Dan
LandOfFree
Metadata access during error handling routines does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Metadata access during error handling routines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metadata access during error handling routines will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3656741