Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-12-15
1998-06-09
Bocure, Tesfaldet
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
327154, 327162, H04L 700
Patent
active
057647100
ABSTRACT:
A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable. Clock-enable conditioning to prevent partial output pulses is merged with the synchronizing function to further reduce latency.
REFERENCES:
patent: 4965814 (1990-10-01), Yoshida et al.
patent: 5155745 (1992-10-01), Sugawara et al.
Cheng Michael B.
Hsiao Charles
Wong Anthony Yap
Wong Belle
Auvinen Stuart T.
Bocure Tesfaldet
Pericom Semiconductor Corp.
Webster Bryan
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