Messaging mechanism for inter processor communication

Details Messaging mechanism for inter processor communication Messaging mechanism for inter processor communication

2011-08-09

2011-08-09

Colin, Carl (Department: 2493)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C714S048000, C714S049000, C714S050000, C714S051000, C714S052000, C714S053000, C714S054000, C714S055000, C714S056000, C714S057000

Reexamination Certificate

active

07996574

ABSTRACT:
An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.

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