Messages signaling interrupt (MSI) processing system

Details Messages signaling interrupt (MSI) processing system Messages signaling interrupt (MSI) processing system

2008-01-29

2008-01-29

Lee, Christopher E. (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

Handling vector

C710S268000, C710S262000, C710S240000

Reexamination Certificate

active

07325084

ABSTRACT:
An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

REFERENCES:
patent: 5988857 (1999-11-01), Ozawa et al.
patent: 6697878 (2004-02-01), Imai
patent: 6968411 (2005-11-01), Gaur et al.
patent: 7103646 (2006-09-01), Suzuki
patent: 2005/0228922 (2005-10-01), Tsao et al.
patent: 2006/0149878 (2006-07-01), Carmichael

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