Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2000-07-31
2003-09-30
Dharia, Rupal (Department: 2189)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S112000, C710S306000
Reexamination Certificate
active
06629179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to intelligent bus subsystems, and more particularly to intelligent PCI bus subsystems that use message signaled interrupts.
2. Description of the Related Art
Modem computer systems typically employ buses to convey information between various parts in the computer systems. For example, computer systems generally include one or more buses to connect a central processing unit (CPU) to a main memory and input/output (I/O) devices for transferring data and control signals. Today, one of the most widely used buses is peripheral component interface (PCI) bus.
With the proliferation of I/O devices such as disk drives, tape drives, printers, scanners, and audio/video devices, the PCI bus is used to connect an increasing number of I/O devices. To accommodate the addition of more I/O devices, conventional computer systems typically provide one or more secondary PCI buses in addition to a primary PCI bus. In intelligent PCI subsystems, a transparent or non-transparent bridge may be used. An intelligent PCI subsystem typically has a CPU on the secondary side and uses a non-transparent bridge to allow more control over device addressing. In such cases, the I/O devices coupled to a secondary PCI are typically not “visible” from the primary PCI bus. For communicating with devices on the primary PCI bus, each secondary PCI bus typically is coupled to the primary PCI bus through a PCI application bridge, which is often referred to as a non-transparent or opaque PCI bridge. A PCI application bridge and devices attached to the PCI bridge form a PCI subsystem.
Conventional bus subsystems such as PCI subsystems typically communicate with a host computer system on the primary PCI bus using an interrupt scheme to control the flow of instruction execution of a host processor. In this scheme, secondary PCI devices attached to a secondary PCI bus communicates an interrupt signal to change the control flow of the host processor. For example, when a secondary PCI device sends data to the host computer system, the secondary PCI device sends an interrupt signal to the host computer system to indicate the completion of data transfer. By using the interrupt scheme, the host processor in the host computer can attend to other tasks while the data is being received. When the interrupt signal from the secondary PCI device is received, the host processor can now process the information received from the device.
Recently, an enhancement to the conventional PCI protocol has been specified. The latest enhancement is specified as an addendum to PCI local bus specification version 2.2 and is commonly known as PCI-X specification. Among other features, PCI specification version 2.2 and the PCI-X specification provide message signaled interrupts (optional for PCI specification version 2.2) to facilitate interrupt processing instead of using interrupt signals. The message signaled interrupts (MSI) are essentially write transactions that enable a device to request service by writing a system-specified message to a system-specified address. In these write transactions, the transaction address specifies the message destination while the transaction data specifies the message. The PCI local bus specification version 2.2 and PCI-X specification are incorporated herein by reference.
In a PCI or PCI-X subsystem, message signaled interrupts are generated as memory writes by individual devices attached to the PCI bus and are forwarded across one or more PCI bridges to a controller associated with the host CPU. Because these write transactions are sent over a PCI bridge as normal memory write transactions, they push through any previously posted write transactions. Since previously posted write transactions are pushed through, the transactions automatically adhere to the PCI transaction ordering rules.
Often, however, a message signaled interrupt that is internally generated by the bridge should not be written until any posted writes that were pending when the interrupt occurred have completed. For example, a secondary PCI agent attached to a secondary PCI bus may be writing data to a primary PCI agent coupled to a primary PCI bus via a PCI bridge. After writing the data, the secondary PCI agent will write a register internal to the bridge, thereby causing the bridge to generate an interrupt message notifying the CPU on the primary PCI bus that the data is available. When the data is posted in the bridge, the write operation has completed from the secondary PCI agent's perspective. Hence, the secondary PCI agent is free to write the register in the PCI bridge to generate the interrupt message to the CPU. In such cases, however, the interrupt message may not reach the CPU prior to the data reaching the primary PCI agent. This may cause error conditions or require the subsystem to provide other ways to guarantee that the write is complete and thereby slow down the performance of the computer system.
Thus, what is needed are a PCI subsystem and a bridge that can ensure completion of posted write operation to a primary PCI agent before sending out an interrupt message. In addition, what is also needed are a PCI subsystem and a bridge that can properly order and transmit message signaled interrupts to a host computer.
SUMMARY OF THE INVENTION
The present invention fills these needs by providing message signaled interrupt generating device and method. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one aspect of the invention, the present invention provides a bridge device for generating message signaled interrupts to indicate completion of write transactions from one or more secondary bus devices to a primary bus device. The bridge device is coupled between a first bus and a second bus. The one or more secondary bus devices are coupled to the second bus and the primary bus device is coupled to the first bus. The bridge device includes a bridge FIFO and control circuitry, a first register, and an interrupt generation logic. The bridge FIFO and control circuitry is arranged to control data transfer between the one or more secondary bus devices and the primary bus device. The bridge FIFO and control circuitry is further configured to store and transfer write data from the one or more secondary bus devices to the primary bus device. The first register is arranged to store a set of interrupt bit numbers. Each of the one or more secondary bus devices is configured to write an interrupt bit number into the first register after completion of a write data transfer to the bridge FIFO and control circuitry to indicate completion of the write data transfer. The interrupt generation logic is coupled to the bridge FIFO and control circuitry and the first register, and is arranged to generate message signaled interrupts in response to the writing of the interrupt bit numbers. In this configuration, the interrupt generation logic generates the message signaled interrupts in the order the write data transfers are posted to the first bus. In addition, each of the message signaled interrupts is generated and posted after all write data transfers associated with the interrupt bit number have been posted to the first bus.
In another aspect of the invention, the present invention provides a method for generating message signaled interrupts to indicate completion of write transactions from one or more secondary bus devices to a primary bus device. The primary bus device is coupled to a first bus and the one or more secondary bus devices are coupled to a second bus. In this method, write data from the one or more secondary bus devices are received and stored for transfer to the primary bus device over the first bus. A set of interrupt bit numbers are received and stored in a first register, wherein each of the one or more secondary bus devices is config
Adaptec, Inc.
Dharia Rupal
Huynh Kim T.
Martine & Penilla LLP
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