Message FIFO buffer controller

Details Message FIFO buffer controller Message FIFO buffer controller

1987-10-15

1989-10-10

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Including signal comparison

365221, 36523002, 365236, G11C 700, G11C 800

Patent

active

048736660

ABSTRACT:
A FIFO (first in first out) control circuit for providing address information to a FIFO memory uses two up counters--one to provide the write address and one to provide the read address. A multiplexer selects which addresses (read or write) are used. Two storage registers are used to temporarily "hold" the output from the counters. This enables the counters to be re-loaded with their original "count" to enable either a re-reading or a re-writing of a message stored in the FIFO memory. Comparators and logic circuitry are used to provide two status output signals, namely full (or not) and empty (or not).

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patent: 4171538 (1979-10-01), Sheller
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patent: 4378594 (1983-03-01), Kenyon
patent: 4433394 (1984-02-01), Torii et al.
patent: 4592019 (1986-05-01), Huange et al.
patent: 4616338 (1986-10-01), Helen et al.
patent: 4694426 (1987-09-01), Mason
Pai, "FIFO RAM Controller Tackles Deep Data Buffering", Computer Design, Aug. 1, 1986, pp. 109-112.
Tunick, "Rich with Logic, Memory ICs Hone their Specialties", Electronic Design, Jun. 11, 1987, pp. 77-86.

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