Mesh geometry for MOS-gated semiconductor devices

Details Mesh geometry for MOS-gated semiconductor devices Mesh geometry for MOS-gated semiconductor devices

1993-11-29

1995-03-21

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257139, 257328, H01L 2910

Patent

active

053998928

ABSTRACT:
A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

REFERENCES:
patent: 4561003 (1985-12-01), Tihanyi et al.
patent: 4833513 (1989-05-01), Sasaki

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