Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-06-12
2007-06-12
Lane, Jack A. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S142000, C711S143000, C711S129000, C711S173000
Reexamination Certificate
active
10867884
ABSTRACT:
In one embodiment, the present invention includes a method for writing data to a disk if inserting the data into a cache, such as a disk cache associated with the disk, would cause a threshold of dirty data in the cache to be met or exceeded. Further, in certain embodiments, the cache may store data according to a first cache policy and a second cache policy. A determination of whether to store data according to the first or second policies may be dependent upon an amount of dirty data in the cache, in certain embodiments. In certain embodiments, the cache may include at least one portion reserved for clean data.
REFERENCES:
patent: 5524234 (1996-06-01), Martinez et al.
patent: 6014728 (2000-01-01), Baror
patent: 2005/0125606 (2005-06-01), Garney
Eschmann Michael K.
Garney John I.
Trika Sanjeev N.
Intel Corporation
Lane Jack A.
Trop Pruner & Hu P.C.
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