Merged data memory testing circuits and related methods which pr

Details Merged data memory testing circuits and related methods which pr Merged data memory testing circuits and related methods which pr

1996-12-23

1999-06-15

Beausoliel, Jr., Robert W.

Excavating

365201, G01R 3128

Patent

active

059128992

ABSTRACT:
An integrated circuit memory device includes first and second input buffers, and first and second input bus lines corresponding to the first and second input buffers. The first input buffer is connected to the first input bus line while a transfer gate is provided between the second input buffer and the second input bus line. The transfer gate connects the second input buffer with the second input bus line during a data input-output operation and disconnects the second input buffer from the second input bus line during a memory test operation. A coupling circuit couples the first and second input bus lines during the memory test operation so that a data value from the first input bus line is inverted and applied to the second input bus line responsive to a first value of an address buffer output during the memory test operation. The data value from the first input line is applied to the second input bus line without inversion responsive to a second value of the address buffer output during the memory test operation. Furthermore, a coupling circuit isolates the first and second input bus lines during the data input-output operation.

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patent: 5537351 (1996-07-01), Suwa et al.
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patent: 5654924 (1997-08-01), Suzuki et al.
patent: 5696720 (1997-12-01), Lee
patent: 5715210 (1998-02-01), Yoo et al.

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