Active solid-state devices (e.g. – transistors – solid-state diode – Including semiconductor material other than silicon or...
Reexamination Certificate
2001-10-19
2004-10-26
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Including semiconductor material other than silicon or...
Reexamination Certificate
active
06809401
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Inventions
The present invention relates to a phase-change memory for storing information by utilizing a reversible phase change which may occur between a crystalline phase and an amorphous phase, a writing apparatus for writing information in the memory, a reading apparatus for reading information from the memory, and writing/reading methods therefor.
2. Description of the Related Art
A phase-change memory in which information can be, recorded or erased by applying electric energy such as an electric current is known. The material used as a recording layer of such a phase-change memory causes reversible change between the crystalline phase and the amorphous phase due to increases in temperature which results from the application of the electric energy. Generally, the electric resistance of the crystalline phase is low, whereas the electric resistance of the amorphous phase is high. The phase-change memory is a non-volatile memory in which binary information is recorded by utilizing the difference in electric resistance between the crystalline phase and the amorphous phase.
In recent years, along with the increase in amount of information to be recorded in a memory, a memory having a larger capacity has been demanded. In order to increase the capacity of a phase-change memory, two suggestions have been provided: (1) the area of a memory cell for recording a binary value a reduced, and a plurality of such memory; cells are arranged in a matrix (increase in surface density) (2) information of a multi-value is stored in a single memory cell. In this specification, the “multi-value” does not include the “binary value”.
Regarding suggestion (1) since there is a limit to a miniaturization process in a production technique such as photolithography, there is also a limit to the increase in surface density. Thus, it is impossible to drastically increase the capacity of a phase-change memory.
A known conventional technique for recording multi-value information in a single memory cell is disclosed in Japanese National Phase PCT Laid-Open Publication No. 11-510317. According to this conventional technique, the resistance value of a recording layer of a memory cell is controlled in a stepwise manner, whereby multi-value information can be stored in the memory cell. However, such a stepwise control of the phase state in a single recording layer involves greater difficulty rather than control of the phase state between the two phase states, i.e., the crystalline phase and the amorphous phase.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a memory includes: a first recording layer for recording information by utilizing a reversible phase change between a crystalline phase and an amorphous phase which occurs due to increases in temperature caused by application of an electric current pulse; and a second recording layer for recording information by utilizing a reversible phase change between a crystalline phase and an amorphous phase which occurs due to increases in temperature caused by application of an electric current pulse, wherein the crystallization temperature of the first recording layer, T
x1
, and the crystallization temperature of the second recording layer, T
x2
, have the relationship T
x1
<T
x2
, the crystallization time of the first recording layer, t
x1
and the crystallization time of the second recording layer, t
x2
, have the relationship t
x1
>t
x2
, and R
a1
+R
a2
, R
a1
+R
c2
, R
c1
+R
a2
, and R
c1
+R
c2
are different from one another where the resistance value of the first recording layer In the amorphous phase is R
a1
the resistance value of the first recording layer in the crystalline phase is R
c1
the resistance value of the second recording layer in the amorphous phase is R
a2
, and the resistance value of the second recording layer in the crystalline phase is R
c2
.
In one embodiment of the present invention, the melting point of the first recording layer, T
m1
, satisfies the relationship 400≦T
m1
(° C.)≦800.
In another embodiment of the present invention, the melting point of the second recording layer, T
m2
, satisfies the relationship 300≦T
m2
(° C.) ≦700.
In still another embodiment of the present invention, the crystallization temperature of the first recording layer, T
x1
, satisfies the relationship 130≦T
x1
,(° C.)≦230.
In still another embodiment of the present invention, the crystallization temperature of the second recording layer, T
x2
, satisfies the relationship 160≦T
x2
(° C.)≦260.
In still another embodiment of the present invention, the crystallization time of the first recording layer, t
x1
, satisfies the relationship 5t
x1
(ns)≦200.
In still another embodiment of the present invention, the crystallization time of the second recording layer, t
x2
, satisfies the relationship 2≦tx
x2
(ns)≦150.
In still another embodiment of the present invention, the first recording layer includes three elements, Ge, Sb, and Te; and the second recording layer includes (Sb-Te)-Ml, where Ml is at least one selected from a group consisting of Ag, In, Ge, Sn, Se, Bi, Au, and Mn.
In still another embodiment of the present invention, the first recording layer is formed on a substrate, and the upper electrode is formed on the second recording layer.
In still another embodiment of the present invention, a lower electrode is formed between the substrate and the first recording layer.
In still another embodiment of the present invention, an intermediate layer is formed between the first recording layer and the second recording layer.
In still another embodiment of the present invention, the specific resistance r
a1
, of the first recording layer in the amorphous phase is 1.0≦r
a1
(&OHgr;·cm)≦1×1×10
7
.
In still another embodiment of the present invention, the specific resistance r
a2
, of the second recording layer in the amorphous phase is 2.0≦r
a2
(&OHgr;·cm)≦2×10
7
.
In still another embodiment of the present invention, the specific resistance r
c1
of the first recording layer in the crystalline phase is 1×10
−3
≦r
c1
(&OHgr;·cm)≦1.0.
In still another embodiment of the present invention, the specific resistance r
c2
of the second recording layer in the crystalline phase is 1×10
−3
≦r
c2
(&OHgr;·cm)≦1.0.
According to another aspect of the present invention, there is provided a writing apparatus for writing information in a memory, the memory including: a first recording layer for recording information by utilizing a reversible phase change between a crystalline phase and an amorphous phase which occurs due to increases in temperature caused by application of an electric current pulse; and a second, recording layer for recording information by utilizing a reversible phase change between a crystalline phase and an amorphous phase which occurs due to increases in temperature caused by application of an electric current pulse, wherein the crystallization temperature of the first recording layer, T
x1
and the crystallization temperature of the second recording layer, T
x2
, have the relationship T
x1
<T
x2
, the crystallization time of the first recording layer, t
x1
and the crystallization time of the second recording layer t
x2
, have the relationship t
x1
>t
x2
, and R
a1
+R
a2
, R
a1
+R
c2
, and R
c1
+R
c2
are different from one another where the resistance value of the first recording layer in the amorphous phase is R
a1
, the resistance value of the first recording layer in the crystalline phase is R
c1
, the resistance value of the second recording layer in the amorphous phase is R
a2
, and the resistance value of the second recording layer in the crystalline phase is R
c2
, and the writing apparatus including: a pulse generator for generating at least first to third electric current pulses and an application section through which the at least first to third electric current pulses are applied to the first recording layer and the second recordin
Kojima Rie
Nishihara Takashi
Yamada Noboru
Flynn Nathan J.
Matsushita Electric - Industrial Co., Ltd.
Quinto Kevin
Renner , Otto, Boisselle & Sklar, LLP
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