Memory write and read control

Details Memory write and read control Memory write and read control

1998-06-02

2001-05-15

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C345S182000, C345S182000, C345S204000, C345S519000, C345S519000, C345S519000, C345S520000, C711S005000, C711S101000, C711S147000, C711S148000, C711S149000, C711S151000, C711S154000, C711S167000, C711S168000

Reexamination Certificate

active

06233658

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory control and in particular to memory write and read control for producing parallel consecutive output data from serial input data.
2. Description of the Related Art
In the field of image processing, image filtering for resolution conversion or enhancing contrast is usually performed by using a filter having parallel input taps and a single output. Therefore, it is necessary to convert serial image data to parallel and consecutive image data.
In general, such parallel consecutive image data can be produced by data tapped from a plurality of line buffers or flip-flops which are connected in serial.
Since undesired input pixel data are, however, sequentially transferred to the parallel input taps of the filter, it is necessary to select desired input pixel data by controlling the line buffers or the flip-flops. Further, there are cases where the filtered pixel data are not sequentially produced. Therefore an output buffer following the filter is needed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory control method and system which can produce consecutive parallel data from serial input data without the need of line buffers or flip-flops.
Another object of the present invention is to provide a memory control method and system which can produce the consecutive parallel image data of a desired image part with simplified configuration.
According to the present invention, a plurality of memories are controlled by write and read controllers. The write controller sequentially writes serial data onto the memories in rotation, and the read controller concurrently reads data from each of the memories to produce a predetermined number of consecutive data in parallel. The serial data may be data blocks or dot data.
According to the present invention, a memory control system is comprised of a frame memory divided into N image memories each indicated by IM
I
, where N and I are an integer and 0≦I≦N−1. Serial image data are sequentially written onto the N image memories in rotation. Then, image data is concurrently read from each of the N image memories depending on a desired read position to produce consecutive N image data in parallel.
The serial image data may be sequentially written onto the N image memories such that K-th image data is written onto an image memory IM
I
so as to satisfy K=N×Q(K/N)+I, where Q(K/N) is a quotient of K/N. P-th image data may be read from the image memory IM
I
such that P is one selected from Q(P/N) and Q(P/N)+1 depending on R(P/N), where R(P/N) is a remainder of P/N.
The image data may be concurrently read from each of the N image memories to produce N image data in parallel, and then the N image data may be sorted to produce consecutive N image data in parallel.
According to the present invention, a memory control system is comprised of a frame memory divided into M×N image memories each indicated by IM
(I, J)
, where M, N, I and J are an integer, 0≦I≦M−1 and 0≦J≦N−1. A write controller sequentially writes serial image data (D(X, Y) onto the M×N image memories in rotation, wherein a set of X and Y indicates a position of a frame of input image data. A read controller concurrently reads image data from each of the M×N image memories depending on a desired read position to produce consecutive M×N image data in parallel.
As described above, the serial data are sequentially written onto the memories in rotation, and are concurrently read from each of the memories to produce a predetermined number of consecutive data in parallel. Therefore, the consecutive parallel image data can be obtained without the need of line buffers, flip-flops or output buffer.
Further, image data is concurrently read from each of the N image memories depending on a desired read position to produce consecutive N image data in parallel. More specifically, the P-th image data may be read from the image memory IM
I
such that P is one selected from Q(P/N) and Q(P/N)+1 depending on R(P/N), where R(P/N) is a remainder of P/N. Therefore, the consecutive parallel image data of a desired image part may be obtained with simplified configuration.


REFERENCES:
patent: 5049865 (1991-09-01), Nakamura et al.
patent: 5307085 (1994-04-01), Nakamura
Unexamined Patent Application Publication (Kokai) No. 60-022878.*
Unexamined Patent Application Publication (Kokai) No. 06-266831.*
Unexamined Patent Application Publication (Kokai) No. 07-192125.*
Japanese Office Action dated Aug. 10, 1999 with cited references Japanese wavy line material and English translation thereof.
European Patent Application No. 0 536 758 A1.
European Patent Application No. 0 530 759 A2.
European Patent Application No. 0368 572.
European Patent Application No. 0 065 365.

Affiliated with

Also associated with

Rating

Memory write and read control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory write and read control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory write and read control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2529276