Memory word-line tracking scheme

Details Memory word-line tracking scheme Memory word-line tracking scheme

2008-05-23

2010-12-07

Phan, Trong (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189090, C365S210100, C365S233100, C365S233140

Reexamination Certificate

active

07848174

ABSTRACT:
A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter.

REFERENCES:
patent: 5784331 (1998-07-01), Lysinger
patent: 5936895 (1999-08-01), Shirley
patent: 5999480 (1999-12-01), Ong et al.
patent: 6128237 (2000-10-01), Shirley et al.
patent: 6297996 (2001-10-01), McClure
patent: 6738296 (2004-05-01), Sung et al.

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