Memory with vectorial access

Details Memory with vectorial access Memory with vectorial access

2001-04-30

2004-03-09

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S202000, C711S217000

Reexamination Certificate

active

06704834

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of the invention is that of parallel memories which constitute an interesting approach for adapting the memory throughput to the computational power which can be installed nowadays on an integrated circuit.
2. Background of the Invention
A parallel memory is a memory which is capable of reading or writing from or to several memory slots in a single access cycle. A Single Instruction Multiple Data (SIMD) is a conventional device that uses parallel memory which can be accessed by all of a device's elementary processors. A SIMD eliminates the need for communication between a device's elementary processors, thereby greatly simplifying the manner of operation and appreciably enhancing the performance of device as compared to a device not equipped with a SIMD.
SIMD machines are mainly used generally to process data organized in tables and in particular for signal processing. Since they execute the same instruction in the same cycle, the elementary processors of an SIMD machine must access aligned and equidistant data components within a single table. These data components may constitute a vector, thereby prompting the name “vectorial access memory.” When processing data, it may be necessary to access vectors with a predetermined orientation with respect to the axes of the single table, or which are, at the very least, parallel to any axis of this table. Likewise, any number of components of the table can separate two successively considered components in the vector. These constraints mean that a vectorial access memory cannot be constructed simply by juxtaposing blocks of RAM memory, the abbreviation standing for the expression “Random Access Memory”. These constraints make it necessary to choose the number of banks carefully and to have address calculators which obey particular rules of installation of the tables in memory. Finally, these constraints require functions for reorganizing components of the vector intervening before writing or after reading to or from the banks.
R. C. Swanson in his article “Interconnections for parallel memories to unscramble pordered vectors” published under the reference IEEE Transactions on computers, vol. C-23, No. 11, November 1974, presents in section II an SIMD calculator model implementing a parallel memory. Swanson shows examples of installing 2D tables in this memory. Swanson also gives a definition of p-ordered vectors and indicates the advantage of flexibility afforded by a prime number of memory banks. Swanson also addresses a vector reordering problem and proposes networks that make it possible to reorder a vector. Swanson does not, however, indicate how to produce a parallel memory. In particular, Swanson does describe howthe addresses applied to the banks are to be calculated. Swanson also only discloses an installation of tables limited to two dimensions so that the proposed network requires that the elements of the reordered vector undergo an excessively complicated process of multiple routings dependent on the initial p-ordering thereof.
SUMMARY OF INVENTION
To provide a more efficient and capable memory access device, the invention proposes an embodiment of a memory with vector access. Accordingly, the subject of the invention is a data memory for data organized as tables, whose structure allows accesses via vectors of N components, and which is addressed according to a specified base of a residue number system, characterized in that it is organized as M memory banks of K slots, each bank, numbered between 0 and M−1, comprising an address calculator for calculating the local address in the relevant bank of a component i of the vector being accessed and in that it comprises a unidirectional network carrying out a permutation of the components of the vector being accessed which consists, either in going from an n-ordered vector to a 1-ordered vector, or in going from a 1-ordered vector to an n-ordered vector, this network furthermore carrying out a translation by a specified value t of the components of the vector being accessed. A memory according to the invention is structured as several banks. The management of the memory locations, such as is allowed by the address calculator of each bank associated with the network for permuting the components of the vectors, is carried out in such a way as to optimize accesses to the memory so as to increase the throughput thereof. The network comprises a number of layers and a number of modes of operation per layer which are determined as a function of a compromise between speed and simplicity. Speed is not compatible with a high number of layers. Simplicity requires a restricted number of modes of operation.


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De-Lei Lee, IEEE Transactions on Computers, vol. 41, No. 4, pp. 499-505, “Architecture of an Array Processor Using a Nonlinear Skewing Scheme”, Apr. 1992.
Roger C. Swanson, IEEE Transactions on Computers, vol. C-23, No. 11, pp. 1105-1115, “Interconnections for Parallel Memories to Unscramble p-Ordered Vectors”, Nov. 1974.
André Seznec, et al., Proceedings of The Annual International Symposium on Computer Architecture, pp. 341-350, “Odd Memory Systems May Be Quite Interesting”, May 16, 1993.
IBM Technical Disclosure Bulletin, vol. 30, No. 9, pp. 226-229, “Residue Generator for an Address Mapping System for a Memory with a Prime Number Stride Capability”, Feb. 1988.

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