Memory with variable levels of interleaving and associated confi

Details Memory with variable levels of interleaving and associated confi Memory with variable levels of interleaving and associated confi

1994-05-23

1997-09-16

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

395872, 711 5, 711115, 711172, G06F 1310, G06F 1200

Patent

active

056689748

ABSTRACT:
A memory having variable interleaving levels and associated configurator circuit which provides for the optimum level of interleaving based on the memory configuration. A number of independently addressable storage modules may be installed in the memory, the modules having various capacities which are usually multiples of a basic capacity. The configurator circuit receives a first field (ALOW) of least significant bits from the address for the desired memory entry and a second field (AHIGH) of bits of greater weight from the memory address. According to the number of the modules present in the memory and their capacities, the configurator circuit generates a module selection signal for selecting from the various modules present and a plurality of signals (MBIT) representing the memory module address bits. The configurator circuit thereby configures the memory with the highest levels of interleaving allowed by the capacity of the modules installed and properly addresses the selected module.

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IBM Technical Disclosure Bulletin, vol. 30, No. 11, Apr. 1988, New York, US; pp. 158-161 `Selectable Memory Card Interleave Scheme`.
Computer Design; vol. 15, No. 24, Nov. 1985, Winchester, US; pp. 93-100; J. Gustafson, et al. `Memory-Mapped VLSI and Dynamic Interleave Improve Performance`, p. 98, left column, line 1 -p. 100, left column, line 16.

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