Memory with storage cells biased in groups

Details Memory with storage cells biased in groups Memory with storage cells biased in groups

2007-05-22

2007-05-22

Dinh, Son (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S189090

Reexamination Certificate

active

11274039

ABSTRACT:
A memory circuit includes a plurality of storage cells (100) arranged in rows and columns thus forming a storage matrix. The storage cells (100) corresponding to the same bit line (21-23) are divided into several groups (60-61) of cells for the same column, these groups having their own biasing circuit (200) in order to act on the difference between the logic level low voltage and the substrate voltage of the link transistors. When a storage cell is not selected, the biasing circuit makes the voltage between source/drain and substrate equal to a negative voltage in order to minimize the leakage current. During a read operation, the substrate voltage and the source/drain voltage are brought back to the same level such that a maximum current will flow when the link transistor is conducting.

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patent: 2001/0038552 (2001-11-01), Ishimaru
patent: 2003/0016552 (2003-01-01), Satomi
Kawaguchi, H., et al.: “Dynamic leadage cut-off scheme for low-voltage SRAM's”; VLSI Circuits, 1998; IEEE, US, Jun. 11, 1998; pp. 140-141, XP010291240; ISBN 0-7803-4766-8.
Kyeong-Sik, Min., et al.: Row-by-Row dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDDSRAM's; International Symposium on Low Power Electronics and Design, NY, NY; ACM, US, Aug. 25, 2003; pp. 66-71; XP010658589; ISBN: 1-58113-682-X.

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