Memory with p-channel cell access transistors

Static information storage and retrieval – Systems using particular element – Flip-flop

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365190, 365230, G11C 1140, G11C 800

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active

046239898

ABSTRACT:
A static random access memory wherein all cells have p-channel access transistors, p-channel driver transistors, and n-channel loads. The access transistors have a width to length ratio which is greater than the width to length ratio of the driver transistors.
The bit lines are precharged close to VSS, and the wordlines are held near VCC in the off state. Thus the operating signals in the array of the SRAM of the present invention are opposite to those in SRAMs of the prior art.

REFERENCES:
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patent: 4132904 (1979-01-01), Harari
patent: 4253162 (1981-02-01), Hollingsworth
patent: 4366560 (1982-12-01), McDermott et al.
patent: 4367538 (1983-01-01), Shimada
patent: 4418402 (1983-11-01), Heagerty et al.
patent: 4467451 (1984-08-01), Moyer
patent: 4507759 (1985-03-01), Yasui et al.
Stewart et al, "A 40 ns CMOS E.sup.2 PROM", IEEE ISSCC, Feb. 11, 1982, pp. 110-111.
Kang et al, "A 30 ns 16K.times.1 Fully Static RAM", IEEE Journal of Solid State Circuits, vol. 16, No. 5, Oct. 1981, pp. 444-448.
Rhodes et al, "A 20 ns, Low Power, 1K.times.4 Static RAM", IEEE Journal of Solid State Circuits, vol. 16, No. 5, Oct. 1981, pp. 594-597.

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